A method for producing a power semiconductor module system includes producing a first and second power semiconductor modules that each have a power semiconductor circuit, connecting first and second contact electrodes to the respective power semiconductor circuits, and partially enclosing the power semiconductor modules in a common housing, wherein the first and second contact electrodes of the two power semiconductor modules are each led through the common housing through a cut-out and where the common housing has first, second and third contacting regions, where the first and second contact electrodes of the first power semiconductor module contact together in the first contacting region, the first and second contact electrodes of the second power semiconductor module contact together in the second contacting region, the second contact electrode of the first power semiconductor module and the second contact electrode of the second power semiconductor module contact together in the third contacting region.

A method for producing a power semiconductor module system includes producing a first and second power semiconductor modules that each have a power semiconductor circuit, connecting first and second contact electrodes to the respective power semiconductor circuits, and partially enclosing the power semiconductor modules in a common housing, wherein the first and second contact electrodes of the two power semiconductor modules are each led through the common housing through a cut-out and where the common housing has first, second and third contacting regions, where the first and second contact electrodes of the first power semiconductor module contact together in the first contacting region, the first and second contact electrodes of the second power semiconductor module contact together in the second contacting region, the second contact electrode of the first power semiconductor module and the second contact electrode of the second power semiconductor module contact together in the third contacting region.

The present invention provides a QFN packaging structure and QFN packaging method. By providing the insulating layer on the outer side of the leads of the QFN packaging structure, a short circuit between the leads and the electromagnetic shielding layer can be prevented. In addition, the grounding lead is exposed from the insulating layer, such that the electromagnetic shielding layer is grounded via the grounding lead, thereby realizing the electromagnetic shielding design of the QFN packaging structure.

The present invention provides a QFN packaging structure and QFN packaging method. By providing the insulating layer on the outer side of the leads of the QFN packaging structure, a short circuit between the leads and the electromagnetic shielding layer can be prevented. In addition, the grounding lead is exposed from the insulating layer, such that the electromagnetic shielding layer is grounded via the grounding lead, thereby realizing the electromagnetic shielding design of the QFN packaging structure.

In some examples, a device comprises a substrate including a notch formed in a surface of the substrate and a semiconductor die positioned in the notch and including an electrochemical sensor on an active surface of the semiconductor die. The device also comprises a chemically inert member abutting the surface of the substrate and including an orifice in vertical alignment with the electrochemical sensor as a result of the semiconductor die being positioned in the notch. The device also comprises a compressed o-ring seal positioned between the chemically inert member and the active surface of the semiconductor die, the compressed o-ring seal circumscribing the electrochemical sensor.

An assembly for a power module includes an electrically isolating base body and first and second electrically conductive structures embedded in the base body. The first and electrically conductive structures are configured to carry different voltages during normal operation of the power module. The first and the second electrically conductive structure each comprise a first region that is not covered by the base body. The first region of the first conductive structure is arranged in a hole of the base body and is retracted with respect to an opening of the hole. The hole is filled with an electrically isolating material that covers the first region of the first conductive structure.

A semiconductor package may include a package substrate, an interposer on the package substrate, photonics modules in the interposer and configured to perform communication based on optical signals, and a semiconductor chip on the interposer. A core substrate of the interposer may include through electrodes and cavities, where the through electrodes may extend from an upper surface of the core substrate to a lower surface of the core substrate. The cavities may extend from the upper surface of the core substrate to an inner portion of the core substrate where the through electrodes are not disposed. One of the photonics modules may be in each of the cavities. Each photonics module may include a photonics integrated circuit chip, and an electronic integrated circuit chip and an optical transmissive layer on an upper surface of the photonics integrated circuit chip.

A semiconductor device includes: a heat dissipation base; a case including an outer peripheral wall that has an inner surface facing an inside of the case and a wiring terminal provided integrally with the outer peripheral wall, the wiring terminal having an inner end portion, which is on one end of the wiring terminal and is exposed to the inside of the case from the inner surface of the outer peripheral wall; a sealing member sealing the inside of the case; and an adhesion member embedded in the inner surface of the case and having an adhesion surface exposed from the inner surface, the adhesion member and the heat dissipation base being on different sides of the inner end portion. The adhesion surface has higher adhesion to the sealing member than the outer peripheral wall.

A device including a semiconductor package, a first passive device, a first barrier structure and a lid structure. The semiconductor package is disposed on a substrate. The first passive device is disposed on the substrate aside the semiconductor package. The first barrier structure is laterally surrounding the first passive device. The lid structure is disposed on the substrate. The first barrier structure is formed with a first sidewall located in between a sidewall of the semiconductor package and a first side surface of the first passive device, and formed with a second sidewall located in between a sidewall of the lid structure and a second side surface of the first passive device. The lengths of the first and second sidewalls are formed to be smaller than a length of the sidewall of the semiconductor package, and greater than a length of the first side surface.

An object is to provide a technique that lowers the self-inductance of a semiconductor device. A semiconductor device includes an insulating substrate having a circuit pattern formed on an upper surface thereof, a semiconductor element mounted on the upper surface of the circuit pattern, and a plurality of electrode terminals each having one end portion bonded to the upper surface of the circuit pattern. The electrode terminals having portions of mutual adjacency of the plurality of electrode terminals are coated with the insulating film having a thickness of less than 100 at least at the portions.