A semiconductor device includes: a first chip including a plurality of first device features and a plurality of first interconnect structures disposed above the first device features; a second chip including a plurality of second device features and a plurality of second interconnect structures disposed above the second device features; and an interposer bonded to the first chip and the second chip, and disposed opposite the first and second device features from the first and second interconnect structures; wherein the interposer includes a plurality of power rails configured to deliver power to the first and second chips.

The present invention relates to a ceramic substrate and a method for manufacturing the same, the ceramic substrate comprising: a ceramic base material; a first electrode pattern and a second electrode pattern formed on the upper and lower surfaces of the ceramic base material; and a third electrode pattern which is formed on the upper surface of the ceramic base material and is spaced apart from the first electrode pattern, wherein a volume ratio obtained by dividing the total volume of the first electrode pattern by the total volume of the second electrode pattern may be 0.9 to 1.1.

Provided are a package substrate and a manufacturing method thereof. The package substrate includes a core board body, a first insulating layer, a circuit structure, and a wiring structure. The core board body is formed with openings connecting two opposite sides of the core board body. The first insulating layer is formed on the two opposite sides of the core board body and filled into the openings. Through holes are formed in the first insulating layer of the openings and are connected to surfaces of the first insulating layer on the two opposite sides of the core board body. The circuit structure includes a circuit layer formed on the surfaces of the first insulating layer on the two opposite sides of the core board body, and conductive pillars formed in the through holes and electrically connected to the circuit layer. The wiring structure is formed on the circuit structure.

A vertical interconnect micro-component adapted for radio frequency signal transmission, preferably for the use in three-dimensional integrated circuits, including: a glass substrate with a first side and a second side opposite to the first side, at least one inner through connector formed in the glass substrate, wherein the inner through connector includes an inner cavity in the glass substrate extending from the first side to the second side of the glass substrate, the inner cavity being fully or partially filled with solid conductor material, and an outer through connector structure formed in the glass substrate and surrounding the at least one inner through connector, the outer through connector structure including one or more outer cavities in the glass substrate extending from the first side to the second side of the glass substrate, the one or more outer cavities each being fully or partially filled with solid conductor material.

An electronic device includes a substrate, a through hole, a first electronic unit, a second electronic unit, a circuit structure, and a third electronic unit. The substrate has a first surface, a second surface opposite the first surface, a first cavity, and a second cavity. A sidewall of the first cavity is connected to the first surface, and a sidewall of the second cavity is connected to the first surface. The through hole extends through the substrate, and a sidewall of the through hole is connected to the first surface and the second surface. The first electronic unit is disposed in the first cavity. The second electronic unit is disposed in the second cavity. The circuit structure is disposed on the first electronic unit and the second electronic unit. The bottom surfaces of the first and second cavities have a roughness ranging from 0 to 2 micrometers.

Embodiments include packages and methods for forming packages which include interposers having a substrate made of a dielectric material. The interposers may also include a redistribution structure over the substrate which includes metallization patterns which are stitched together in a patterning process which includes multiple lateral overlapping patterning exposures.

A package structure including a semiconductor die, a redistribution layer, a plurality of antenna patterns, a die attach film, and an insulating encapsulant is provided. The semiconductor die have an active surface and a backside surface opposite to the active surface. The redistribution layer is located on the active surface of the semiconductor die and electrically connected to the semiconductor die. The antenna patterns are located over the backside surface of the semiconductor die. The die attach film is located in between the semiconductor die and the antenna patterns, wherein the die attach film includes a plurality of fillers, and an average height of the die attach film is substantially equal to an average diameter of the plurality of fillers. The insulating encapsulant is located in between the redistribution layer and the antenna patterns, wherein the insulating encapsulant encapsulates the semiconductor die and the die attach film.

Provided is a package substrate. In a manufacturing method thereof, by combining two extremely thin substrates to be processed on opposite sides of a carrier (and/or a support member), a first circuit layer and a second circuit layer are respectively formed on opposite sides of a core layer of the substrate. Therefore, the structural thickness required for the manufacturing process is increased such that the processability of the ultra-thin substrates is not limited by the equipment performance, thereby eliminating the need for specialized equipment and significantly reducing processing costs.

A semiconductor device includes first and second conductive layers, a first epitaxial structure and a first via structure. The first conductive layer extends along a first direction, and provides a first reference voltage signal. The second conductive layer extends along the first direction, and is separated from the first conductive layer along a second direction. The first epitaxial structure is disposed between the first conductive layer and the second conductive layer, and has a first width along the first direction. The first via structure is disposed between the first conductive layer and the second conductive layer, and transmits the first reference voltage signal from the first conductive layer through the second conductive layer to the first epitaxial structure. The first via structure has a second width along the first direction. The second width is approximately equal to or larger than twice of the first width.

In a first insulating layer, a through-hole penetrates the first insulating layer in the thickness direction. A first conductor pattern is on a first surface that is one surface of the first insulating layer. The first conductor pattern closes the opening of the through-hole on the side of the first surface. A first connection conductor is in the through-hole. The first connection conductor is connected to the first conductor pattern, and the dimension of the first connection conductor in the thickness direction is smaller than the dimension of the first insulating layer in the thickness direction. A metal element with the maximum content in the first conductor pattern is the same as a metal element with the maximum content in the first connection conductor.