In one example, a semiconductor device comprises a first substrate comprising a first conductive structure, a first body over the first conductive structure and comprising an inner sidewall defining a cavity in the first body, a first interface dielectric over the first body, and a first internal interconnect in the first body and the first interface dielectric, and coupled with the first conductive structure. The semiconductor device further comprises a second substrate over the first substrate and comprising a second interface dielectric, a second body over the second interface dielectric, and a second conductive structure over the second body and comprising a second internal interconnect in the second body and the second interface dielectric. An electronic component is in the cavity, and the second internal interconnect is coupled with the first internal interconnect. Other examples and related methods are also disclosed herein.

A semiconductor device assembly comprises an RDL including an external surface with external contacts, an internal surface with internal contacts, and conductors coupling the internal contacts to the external contacts. The assembly further includes a device connection layer having a first surface with first contact pads, a second surface with second contact pads, first conductive structures electrically coupling each of the first contact pads to a corresponding second contact pad, and a second plurality of conductive structures electrically coupling each of a first subset of the second plurality of contact pads to a corresponding contact pad of a second subset of the second plurality of contact pads. The assembly further includes stacks of semiconductor devices disposed between the RDL and the device connection layer, each stack in a cavity in a monolithic glass structure. The stacks electrically couple internal contacts to the first contact pads through TSVs in the stacks.

A semiconductor device structure is provided. The semiconductor device structure includes an interconnection structure over a semiconductor substrate and a conductive pillar over the interconnection structure. The conductive pillar has a protruding portion extending towards the semiconductor substrate from a lower surface of the conductive pillar. The semiconductor device structure also includes an upper conductive via between the conductive pillar and the interconnection structure and a lower conductive via between the upper conductive via and the interconnection structure. The lower conductive via is electrically connected to the conductive pillar through the upper conductive via. The conductive pillar extends across opposite sidewalls of the upper conductive via and opposite sidewalls of the lower conductive via. A top view of an entirety of the second conductive via is separated from a top view of an entirety of the protruding portion.

In an embodiment, a package includes an interposer; a first integrated circuit device attached to the interposer, wherein the first integrated circuit device includes a die and a heat dissipation structure, the die having an active surface facing the interposer and an inactive surface opposite to the active surface, the heat dissipation structure attached to the inactive surface of the die and including a plurality of channels recessed from a first surface of the heat dissipation structure, the first surface of the heat dissipation structure facing away from the die; and an encapsulant disposed on the interposer and laterally around the die and the heat dissipation structure, wherein a top surface of the encapsulant is coplanar with the top surface of the heat dissipation structure.

A package structure and a manufacturing method thereof are disclosed. The structure includes at least one semiconductor die, a redistribution layer disposed on the at least one semiconductor die, and connectors there-between. The connectors are disposed between the at least one semiconductor die and the redistribution layer, and electrically connect the at least one semiconductor die and the redistribution layer. The redistribution layer includes a dielectric layer with an opening and a metallic pattern layer disposed on the dielectric layer, and the metallic pattern layer includes a metallic via located inside the opening with a dielectric spacer surrounding the metallic via and located between the metallic via and the opening.

A component carrier having a stack with at least one electrically insulating layer structure and at least two electrically conductive layer structures, and at least one electrically conductive element. The at least one electrically conductive element passes through the at least one electrically insulating layer structure, preferably in a stacking direction. The at least one electrically conductive element comprises an electrically conductive paste provided in a cavity being located at least partially within the at least one electrically insulating layer structure. The electrically conductive paste is in contact with the at least two electrically conductive layer structures, wherein the center of gravity of one vertical extremity of the at least one electrically conductive element is misaligned with respect to the center of gravity of the opposed other vertical extremity of the at least one electrically conductive element.

A packaging device is provided. The packaging device includes a die disposed over a laminate, the die comprising a first via structure, and an interposer disposed between the die and the laminate. The interposer includes a second via structure. The packaging device also includes a lid disposed over the interposer and covering the die, a first patterned conductive layer disposed between the die and the interposer, and between the lid and the interposer; and a second patterned conductive layer disposed between the laminate and the interposer. The first patterned conductive layer includes a bonding structure electrically and thermally connected to the first via structure and the second via structure.

A semiconductor package includes a package substrate having bond fingers, at least one semiconductor chip on the package substrate, the at least one semiconductor chip having chip pads on an upper surface thereof, and conductive wires electrically connecting the chip pads and the bond fingers, wherein the package substrate includes an insulating layer having an upper surface and a lower surface opposite the upper surface, the insulating layer having a recess of a predetermined depth from the upper surface of the insulating layer, upper circuit wirings having pad patterns in the insulating layer and extending such that at least a portion of each of the pad patterns is exposed from a bottom surface of the recess, and a respective plating pattern on the portion of each of the pad patterns that is exposed, the respective plating pattern provided as the bond finger.

An optical module includes a wiring substrate, electronic components mounted on the wiring substrate, and a waveguide component mounted on the wiring substrate and connecting the electronic components to each other. The waveguide component includes a waveguide substrate including an optical waveguide, a first surface, and a second surface opposite the first surface. A photonic integrated circuit element is mounted on the first surface of the waveguide substrate and optically connected to the optical waveguide. An electrical integrated circuit element is mounted on the second surface of the waveguide substrate and electrically connected to the photonic integrated circuit element.

A system-in-package includes an interposer substrate having a first side and a second side opposite the first side, and a redistribution layer disposed on the first side. The redistribution layer includes a plurality of contact pads and a plurality of interconnections disposed on the first side. The plurality of interconnections is electrically connected to a plurality of terminals disposed on the second side opposite the first side. A first semiconductor die is disposed on the first side and electrically coupled to a first of the plurality of contact pads and a first of the plurality of interconnections disposed on the first side of the interposer substrate. A second semiconductor die is disposed on the first side. The second semiconductor die is electrically coupled to a second of the plurality of contact pads and a second of the plurality of interconnections disposed on the first side of the interposer substrate.