Patent classifications
H10W70/095
Wire bonding directly on exposed conductive vias and interconnects and related systems and methods
Stacked semiconductor devices, and related systems and methods, are disclosed herein. In some embodiments, the stacked semiconductor device includes a package substrate having at least a first layer and a second layer, an interconnect extending through the package substrate, a stack of dies carried by the package substrate, and one or more wirebonds electrically coupling the stack of dies to package substrate. Each of the layers of the package substrate can include a section of the interconnect with a frustoconical shape. Each of the sections can be directly coupled together. Further, the section in an uppermost layer of the package substrate is exposed at an upper surface of the package substrate. The wirebonds can be directly coupled to the exposed surface of the uppermost section.
Packaging structure and manufacturing method thereof
The present invention provides a packaging structure and a manufacturing method thereof. The packaging structure includes a lower package, an upper package and a first redistribution stack layer disposed between the lower package and the upper package, wherein the first redistribution stack layer is electrically connected to the lower package and the upper package; the lower package includes a prefabricated substrate and a first plastic packaging layer surrounding the periphery of the prefabricated substrate; and the minimum line width/line spacing of the first redistribution stack layer is less than the minimum line width/line spacing of the prefabricated substrate. The lower package includes the prefabricated substrate and the first redistribution stack layer is disposed above the prefabricated substrate and has the minimum line width/line spacing less than that of the prefabricated substrate, so that more chips and/or device packages are integrated in the packaging structure.
Through molding contact enabled EMI shielding
Disclosed are examples of multi-die modules that includes a die (e.g., a power amplifier) and an adjacent die placed side-by-side and bonded onto a substrate with a mold compound. The die (e.g., a switch or a low noise amplifier) may be double EMI shielded to minimize or even eliminate EMI/noise coupling with the adjacent die (e.g., switch, low noise amplifier, etc.). Another mold compound, which can be thermally conductive, may be provided to improve transfer of heat away from the die and/or the adjacent die.
Substrate and preparation method thereof, integrated passive device, and electronic apparatus
Provided are a substrate, a method for preparing the substrate, an integrated passive device, and an electronic apparatus. The method for preparing the substrate includes: providing a base substrate including at least one blind via, wherein the base substrate includes a first surface and a second surface disposed oppositely, a blind via extends from a first surface side to interior of the base substrate, and an aperture of the blind via gradually decreases in a direction from the first surface to the second surface; forming a connection electrode in the blind via; thinning the base substrate along a direction from the second surface to the first surface, wherein the blind via on the thinned base substrate forms a via hole penetrating the base substrate.
Semiconductor device having contact plug
An apparatus that includes a first conductive pattern positioned at a first wiring layer and extending in a first direction, a second conductive pattern positioned at a second wiring layer located above the first wiring layer and extending in a second direction, and a contact plug connecting the first conductive pattern with the second conductive pattern. The contact plug includes a lower conductive section contacting the first conductive pattern and an upper conductive section contacting the second conductive pattern. The width of the lower conductive section on a first boundary between the lower and upper conductive sections in the first direction is greater than the width of the upper conductive section on the first boundary in the first direction and the width of the second conductive pattern on a second boundary between the contact plug and the second conductive pattern in the first direction.
Pad design for reliability enhancement in packages
A package includes a corner, a device die, a molding material molding the device die therein, and a plurality of bonding features. The plurality of bonding features includes a corner bonding feature at the corner, wherein the corner bonding feature is elongated. The plurality of bonding features further includes an additional bonding feature, which is non-elongated.
UNIFORM SEED LAYER FOR THROUGH HOLES IN GLASS SUBSTRATES
Embodiments disclosed herein include an apparatus that comprises a substrate, and the substrate includes glass. In an embodiment, an opening is provided through a thickness of the substrate, and a layer is along a sidewall of the opening. In an embodiment, the layer comprises a polymer and an electrical conductor that comprises carbon. In an embodiment, a via is provided in the opening, and the via is an electrically conductive material.
GLASS SUBSTRATE PROCESSING METHOD, AND ELECTRONIC DEVICE MANUFACTURING METHOD
A glass substrate processing method includes forming a through hole by irradiating a glass substrate with ultraviolet-wavelength pulse laser light; forming a modified section by irradiating a region surrounding the through hole with ultrashort pulse laser light, the region extending over a predetermined range from an inner wall of the through hole; and etching the glass substrate with an etchant to increase a hole diameter of the through hole, the etchant providing an etching rate for etching the modified section higher than an etching rate for etching the glass substrate excluding the modified section.
HIGH-INTEGRATED SUBSTRATE MANUFACTURING METHOD THEREFOR, AND POWER MODULE
The present invention is directed to a high-integrated substrate, which is laminated and stacked by means of a plurality of prefabricated boards. Electrical connections between prefabricated boards are realized by means of electrical connectors, thereby reducing solder joints and connective paths between layers; in addition, by disposing the element in the substrate, the space utilization rate of the substrate in the plane and the height direction is further improved; on the other hand, in the present invention, the part of the magnetic core is arranged in the accommodating space, and the accommodating space is in communication with the external space by means of the exhaust channel, so as to reduce the working temperature of the magnetic core assembly and improve the working performance of the magnetic core assembly, and at the same time, the reliability of the substrate in the service process is improved.
SEMICONDUCTOR DEVICE WITH MULTIPLE DIES
A semiconductor device includes a first die having ports and a second die having ports. The semiconductor device includes a multi-layer package substrate. The multi-layer package substrate includes a first layer patterned to include pads for the ports of the first die and the second die and a second layer patterned to provide vias between the pads for the ports of the first die and pads for the ports of the second die and a third layer of the multi-layer package substrate. The third layer is patterned to provide traces that couple the vias coupled to ports of the first die to vias coupled to ports of the second die to couple the first die to the second die, the traces of the third layer having a width. The multi-layer package substrate also includes a fourth layer underlying the third layer and a ground plane underlying the fourth layer.