A package structure includes a circuit substrate, a semiconductor package, a lid structure, a passive device and a barrier structure. The semiconductor package is disposed on and electrically connected to the circuit substrate. The lid structure is disposed on the circuit substrate covering the semiconductor package. The lid structure is attached to the circuit substrate through an adhesive material. The passive device is disposed on the circuit substrate in between the semiconductor package and the lid structure. The barrier structure is separating the passive device from the lid structure and the adhesive material, and the barrier structure is in contact with the adhesive material.

Provided is a package structure, including a substrate, a chip on the substrate in a flip-chip manner, the chip including a circuit layer, and a side heat dissipator on a side of the chip, the side heat dissipator comprising a heat conduction material, wherein the side heat dissipator is electrically connected to the circuit layer.

Semiconductor three-dimensional integrated circuit packages and methods of forming the same are disclosed herein. A method includes bonding a semiconductor chip package to a substrate and depositing a thermal interface material on the semiconductor chip package. A thermal lid may be placed over and adhered to the semiconductor chip package by the thermal interface material. The thermal lid includes a wedge feature interfacing the thermal interface material. The thermal lid may be adhered to the semiconductor chip package by curing the thermal interface material.

A semiconductor module includes a laminate substrate including an insulating plate and first and second circuit boards on an upper surface of the insulating plate, the first semiconductor device on an upper surface of the first circuit board, a first main terminal, and a first metal wiring board that electrically connects the first semiconductor device to the first main terminal. The first metal wiring board has a first bonding section bonded to an upper surface electrode of the first semiconductor device, a second bonding section bonded to an upper surface of the second circuit board, a first coupling section that couples the first bonding section to the second bonding section, a first raised section that rises upward from an end portion of the second bonding section. The first raised section has an upper end that is electrically connected to the first main terminal.

A semiconductor package includes a wiring board including at least one pair of connection structures electrically connecting at least one pair of differential signal transmission lines and at least one pair of differential signal transmission terminals, respectively. The at least one pair of connection structures includes first via structures staggered in a vertical direction, at least one first connection line electrically connecting the first via structures, second via structures staggered in the vertical direction, and at least one second connection line electrically connecting the second via structures. The at least one first connection line is spaced apart from the at least one second connection line in the vertical direction and electrically insulated therefrom, and intersects the at least one second connection line in the vertical direction.

In an embodiment, a package includes an encapsulant laterally surrounding a first integrated circuit device and a second integrated circuit device, wherein the first integrated circuit device includes a die and a heat dissipation structure over the die; a sealant disposed over the heat dissipation structure; an adhesive disposed over the second integrated circuit device; and a lid disposed over the sealant and the adhesive, wherein the lid includes a first cooling passage and a second cooling passage, the first cooling passage including an opening at a bottom of the lid and aligned to the heat dissipation structure, the second cooling passage including channels aligned to the second integrated circuit device and being distant from the bottom of the lid.

To suppress flowing out of an adhesive to the outside of a prescribed region in a semiconductor package in which a substrate is bonded to a support by the adhesive. A semiconductor package includes a substrate, a semiconductor chip, a support, and a first adhesive. In this semiconductor package, the semiconductor chip is placed on a substrate flat surface of the substrate and electrically connected to the substrate. Further, in the semiconductor package, a part of the first adhesive flows into a gap between the substrate flat surface and the semiconductor chip, and adheres the substrate to the support.

To suppress flowing out of an adhesive to the outside of a prescribed region in a semiconductor package in which a substrate is bonded to a support by the adhesive. A semiconductor package includes a substrate, a semiconductor chip, a support, and a first adhesive. In this semiconductor package, the semiconductor chip is placed on a substrate flat surface of the substrate and electrically connected to the substrate. Further, in the semiconductor package, a part of the first adhesive flows into a gap between the substrate flat surface and the semiconductor chip, and adheres the substrate to the support.

A device including a semiconductor package, a first passive device, a first barrier structure and a lid structure. The semiconductor package is disposed on a substrate. The first passive device is disposed on the substrate aside the semiconductor package. The first barrier structure is laterally surrounding the first passive device. The lid structure is disposed on the substrate. The first barrier structure is formed with a first sidewall located in between a sidewall of the semiconductor package and a first side surface of the first passive device, and formed with a second sidewall located in between a sidewall of the lid structure and a second side surface of the first passive device. The lengths of the first and second sidewalls are formed to be smaller than a length of the sidewall of the semiconductor package, and greater than a length of the first side surface.

In one example, an electronic device includes a first substrate and a second substrate. The first substrate includes a substrate first side, a substrate second side, and a first conductive structure. An inner electronic component is coupled to the first conductive structure proximate to the substrate second side. An outer electronic component is coupled to the first conductive structure proximate to the substrate first side. The outer electronic component includes a body and a groove in the body configured to couple with an external interconnect. Inner interconnects couple the first substrate to the second substrate. The first substrate, the second substrate, the inner electronic component, and the outer electronic component are in a stacked configuration. The inner electronic component is interposed between the first substrate and the second substrate. Other examples and related methods are also disclosed herein.