A device including a semiconductor package, a first passive device, a first barrier structure and a lid structure. The semiconductor package is disposed on a substrate. The first passive device is disposed on the substrate aside the semiconductor package. The first barrier structure is laterally surrounding the first passive device. The lid structure is disposed on the substrate. The first barrier structure is formed with a first sidewall located in between a sidewall of the semiconductor package and a first side surface of the first passive device, and formed with a second sidewall located in between a sidewall of the lid structure and a second side surface of the first passive device. The lengths of the first and second sidewalls are formed to be smaller than a length of the sidewall of the semiconductor package, and greater than a length of the first side surface.

The present disclosure relates to a power semiconductor module including: a carrier; a plurality of semiconductor dies mounted onto the carrier; a housing including a frame enclosing the carrier circumferentially; a first external connection electrically connected to a first subset of the semiconductor dies, the first external connection protruding laterally from the housing at a first level; and an insert including an electrically isolating material and a second external connection mounted onto the electrically isolating material. The insert is at least partially mounted to the frame and at least partially covers the carrier and/or the first subset of the plurality of semiconductor dies. The second external connection is connected to a second subset of the plurality of semiconductor dies. The second external connection protrudes from the housing.

Examples of devices for providing cooling solutions are described. One example device includes a boilerplate, a printed circuit board (PCB), one or more integrated circuit (IC) chips placed on the PCB, a thermal interface material (TIM), and one or more gaskets. The TIM is placed between the boilerplate and at least one IC chip of the one or more IC chips. The TIM is coupled to a surface of at least the IC chip that faces the boilerplate. The one or more gaskets are placed between the boilerplate and the PCB and encompassing the TIM. The one or more gaskets are configured to seal the at least one IC chip to provide a protective barrier for the TIM.

Provided is an electronic device including a substrate, a first metal layer, an electronic component, a cover layer, and an adhesive layer. The first metal layer is formed on the substrate. The electronic component is disposed on the substrate and electrically connected to the first metal layer. The adhesive layer is adhered to the substrate and the cover layer.

Microelectronic integrated circuit package structures include a package structure comprising a first die on a first dielectric material and a second die on second dielectric material, where the first die is adjacent to the second die. A third die is below the first die and is hybrid bonded to the first die. a fourth die is below the second die, and is hybrid bonded to the second die. A layer comprising nitrogen and silicon is directly on top surfaces of the first die and the second die. A fill dielectric material is between the first die and the second die, and a lid over the fill dielectric material.

An electronic device includes a semiconductor die having a side, and a cap including a first portion spaced apart from the side of the semiconductor die to define a cavity over a portion of the side of the semiconductor die, and a second portion attached to the side of the semiconductor die and extending from the side of the semiconductor die to the first portion, wherein one of the first and second portions has an opening.

An IC chip. The IC chip has an IC substrate, at least one IC functional layer on the substrate, and an etching hole that penetrates the IC functional layer from an outer side through to the substrate. A metal seal is arranged between a region of the IC functional layer and the etching hole.

Disclosed herein are microelectronic assemblies, as well as related apparatuses and methods. In some embodiments, a microelectronic assembly may include a substrate; a lid surrounding an individual die, wherein the lid includes a planar portion and two or more sides extending from the planar portion, and wherein the individual die is electrically coupled to the substrate by interconnects; and a material surrounding the interconnects and coupling the two or more sides of the lid to the substrate.

Disclosed herein are microelectronic assemblies, as well as related apparatuses and methods. In some embodiments, a microelectronic assembly may include a substrate; a lid surrounding an individual die, wherein the lid includes a planar portion and two or more sides extending from the planar portion, and wherein the individual die is electrically coupled to the substrate by interconnects; and a material surrounding the interconnects and coupling the two or more sides of the lid to the substrate.

An embodiment semiconductor device includes an interposer, a semiconductor die electrically connected to the interposer, an integrated passive device die electrically connected to the interposer, the integrated passive device die including two or more seal rings, and a first alignment mark formed on the integrated passive device die within a first area enclosed by a first one of the two or more seal rings. The integrated passive device die may further include two or more integrated passive devices located within respective areas enclosed by respective ones of the two or more seal rings. Each of the two or more integrated passive devices may include electrical connections that are formed as a plurality of micro-bumps, and the first alignment mark may be electrically isolated from the electrical connections, and the first alignment mark and the electrical connections may share a common material.