An apparatus comprising a first substrate, a dam structure disposed on a first side of the first substrate, and an integrated circuit (IC) memory chip coupled to the first side of the first substrate by a plurality of first conductive members. A second substrate is coupled to a second side of the first substrate by a plurality of second conductive members. A lid coupled to the second substrate encloses the IC memory chip and the first substrate. A thermal interface material (TIM) is coupled between the lid and the dam structure.

Implementations of a semiconductor package may include a die; a first pad and a second pad, the first pad and the second pad each including a first layer and a second layer where the second layer may be thicker than the first layer. At least a first conductor may be directly coupled to the second layer of the first pad; at least a second conductor may be directly coupled to the second layer of the second pad; and an organic material may cover at least the first side of the die. The at least first conductor and the at least second conductor extend through openings in the organic material where a spacing between the at least first conductor and the at least second conductor may be wider than a spacing between the second layer of the first pad and the second layer of the second pad.

A semiconductor package includes an interposer that includes a plurality of lower pads and a plurality of upper pads, a first semiconductor chip on the interposer, where the first semiconductor chip includes a first side portion and a second side portion, where the first semiconductor chip includes a first physical layer in a first region that is adjacent to the first side portion and a second physical layer in a second region that is adjacent to the second side portion, a photonic integrated circuit (IC) chip including a plurality of first through vias that at least partially overlap the second region, and an electronic IC chip on the photonic IC chip, where the electronic IC chip includes a third physical layer that at least partially overlaps the second region.

A method includes bonding a first package component over a second package component. The second package component includes a plurality of dielectric layers, and a plurality of redistribution lines in the plurality of dielectric layers. The method further includes dispensing a stress absorber on the second package component, curing the stress absorber, and forming an encapsulant on the second package component and the stress absorber.

A semiconductor package includes a semiconductor die, a redistribution circuit structure, a supporting structure and a protective layer. The redistribution circuit structure is located on and electrically coupled to the semiconductor die. The supporting structure is located on an outer surface of the redistribution circuit structure, wherein the supporting structure is overlapped with at least a part of the semiconductor die or has a sidewall substantially aligned with a sidewall of the semiconductor die in a vertical projection on the redistribution circuit structure along a stacking direction of the redistribution circuit structure and the supporting structure. The protective layer is located on the supporting structure, wherein the supporting structure is sandwiched between the protective layer and the redistribution circuit structure.

A semiconductor package including a dielectric layer on a substrate and having an opening that partially exposes a top surface of the substrate, a capacitor chip on the substrate and in the opening of the dielectric layer, connection terminals between the substrate and the capacitor chip and connecting the substrate and the capacitor chip to each other, dielectric patches on the substrate and in the opening of the dielectric layer, and an under-fill filling a space between the substrate and the capacitor chip may be provided. The space between the substrate and the capacitor chip includes a first region, a second region, and a third region between the first and second regions. The connection terminals are on the first region and the second region. The dielectric patches are on the third region.

In examples, a semiconductor package includes a solder joint pillar within a solder joint. The solder joint couples various structures of the semiconductor package.

An electronic device includes a conductive lead, a semiconductor die, a package structure enclosing the semiconductor die and a portion of the conductive lead, and a non-conductive die attach film extending between the conductive lead and the semiconductor die and having a thickness less than 50 m. A method of fabricating an electronic device includes singulating portions of a non-conductive die attach film on a carrier, partially singulating prospective die areas from a front side of a wafer, removing wafer material from a back side of the wafer to separate a semiconductor die from the wafer, and attaching a backside the semiconductor die to a singulated portion of the non-conductive die attach film on the carrier.

A semiconductor device includes a gate pattern disposed over a lower structure, and including a gate electrode region and a gate pad region extending from the gate electrode region; and a vertical channel semiconductor layer having a side surface facing the gate electrode region of the gate pattern. The gate pad region includes a first pad region having a thickness greater than a thickness of the gate electrode region. The first pad region includes an upper surface, a lower surface opposing the upper surface, and an outer side surface. The outer side surface has a lower outer side surface and an upper outer side surface, divided from each other by a boundary portion. The lower outer side surface extends from the lower surface, and a connection portion of the lower outer side surface and the lower surface has a rounded shape.

An electrically non-conducting film (109) comprising an oligomer comprising an arylene or heteroarylene repeating unit is disposed between a chip (105), e.g. a flip-chip, and a functional layer (101), e.g. a printed circuit board, electrically connected to the chip by electrically conducting interconnects (107). The oligomer may be crosslinked.