A method includes bonding a tier-1 device die to a carrier, forming a first gap-filling region to encapsulate the tier-1 device die, forming a first redistribution structure over and electrically connected to the tier-1 device die, and bonding a tier-2 device die to the tier-1 device die. The tier-2 device die is over the tier-1 device die, and the tier-2 device die extends laterally beyond a corresponding edge of the tier-1 device die. The method further includes forming a second gap-filling region to encapsulate the tier-2 device die, removing the carrier, and forming a through-dielectric via penetrating through the first gap-filling region. The through-dielectric via is overlapped by, and is electrically connected to, the tier-2 device die. A second redistribution structure is formed, wherein the first redistribution structure and the second redistribution structure are on opposing sides of the tier-1 device die.

A semiconductor device assembly can include an assembly semiconductor die having a top surface with a first and a second assembly communication element thereat. The semiconductor device assembly can further include a semiconductor die stack coupled to the top surface. The die stack can include a first and a second semiconductor die, each having a top surface perpendicular to the top surface of the assembly semiconductor die. Further, the first semiconductor die can have a first die communication element aligned with and configured to directly communicate with the first assembly communication element, and the second semiconductor die can have a second die communication element aligned with and configured to directly communicate with the second assembly communication element.

A memory device includes a first case, a second case coupled to the first case, a mid plate placed in an inner space between the first and second cases, a first memory module between the first case and the mid plate, including a first module substrate and at least one first electronic chip on the first module substrate, and a second memory module between the second case and the mid plate, including a second module substrate and at least one second electronic chip on the second module substrate, wherein the mid plate includes a base unit, a first rib structure extending from the base unit to electrically connect the mid plate to the first module substrate, and a second rib structure spaced apart from the first rib structure to electrically connect the mid plate to the first module substrate.

A semiconductor device according to the present embodiment includes a resin layer, ink, and a film. The ink is provided on an upper surface of the resin layer. The film coats the resin layer and the ink. Surface roughnesses of the film are different between in a first region where the ink is provided and in a second region where the ink is not provided.

A semiconductor device including a through-via having an improved heat dissipation characteristic and a semiconductor package including the semiconductor device are provided. The semiconductor device includes a semiconductor substrate, an active layer on a lower surface of the semiconductor substrate, a through-via passing through the semiconductor substrate and extending, and a heat dissipation layer including an aluminum nitride (AlN) layer and disposed on an upper surface of the semiconductor substrate to surround a side surface of an upper portion of the through-via.

Various aspects of this disclosure provide a semiconductor device and a method of manufacturing a semiconductor device. As a non-limiting example, various aspects of this disclosure provide a semiconductor device comprising a stacked die structure and a method of manufacturing thereof.

A stacked memory device includes a first die including a first region and a second region, the first die being on a plane defined by a first direction and a second direction, and a die group stacked on the second region. A first layer is disposed beneath the first region, the first layer controlling transmission of signals between the die group and a processor through a plurality of channels, and an empty space is provided over on the first region.

Embodiments of the invention include molded modules and methods for forming molded modules. According to an embodiment the molded modules may be integrated into an electrical package. Electrical packages according to embodiments of the invention may include a die with a redistribution layer formed on at least one surface. The molded module may be mounted to the die. According to an embodiment, the molded module may include a mold layer and a plurality of components encapsulated within the mold layer. Terminals from each of the components may be substantially coplanar with a surface of the mold layer in order to allow the terminals to be electrically coupled to the redistribution layer on the die. Additional embodiments of the invention may include one or more through mold vias formed in the mold layer to provide power delivery and/or one or more faraday cages around components.

This document discloses techniques, apparatuses, and systems for providing a semiconductor device assembly with a substrate for vertically assembled semiconductor dies. A semiconductor assembly is described that includes a semiconductor die coupled to a substrate such that an active surface of the semiconductor die is substantially orthogonal to a top surface of the substrate. The substrate includes a surface having a recessed slot at which a side surface of the semiconductor die couples. The semiconductor die includes a contact pad that couples to a contact pad at the recessed slot. In doing so, the techniques, apparatuses, and systems herein enable a robust and cost-efficient semiconductor device to be assembled.

A semiconductor package includes a silicon die including a first die surface coupled to a package substrate, a second die surface opposite to the first die surface, and at least one die sidewall orthogonal to the first die surface and the second die surface, and a mold layer including a first mold surface, a second mold surface opposite to the first mold surface, and at least one mold sidewall orthogonal to the first mold surface and the second mold surface, the at least one mold sidewall being disposed along the at least one die sidewall, and the mold layer further including a power conductive corridor extending from the first mold surface and coupled to the package substrate through the first mold surface. The semiconductor package further includes a first stacked device coupled to the first die surface and to the power conductive corridor through the first mold surface.