An exemplary method includes at a bonding temperature, bonding a semiconductor chip to an organic laminate substrate using solder; without cooldown from the bonding temperature to room temperature, at an underfill dispense temperature, dispensing underfill between the semiconductor chip and the organic laminate substrate; and curing the underfill within a range of temperatures above the underfill dispense temperature. Another exemplary method includes depositing a first solder on pads of an organic laminate substrate; contacting a second solder on pillars of a semiconductor chip to the first solder on the pads of the organic laminate substrate; and solder bonding the semiconductor chip to the organic laminate substrate.

A disclosed system is configured to bond a chip to a substrate and includes a chip processing subsystem that is configured to receive the chip and to expose the chip to a first plasma, and a substrate processing subsystem that is configured to receive the substrate and to expose the substrate to a second plasma. The system further includes a bonding subsystem that is configured to align the chip with the substrate, to force the chip and the substrate into direct mechanical contact with one another by application of a compressive force, and to apply heat to at least one of the chip or the substrate. Application of the compressive force and the heat thereby bonds the chip to the substrate. The first and second plasmas may include H.sub.2/N.sub.2, H.sub.2/Ar, H.sub.2/He, NH.sub.3/N.sub.2, NH.sub.3/Ar, or NH.sub.3/He and the chip and substrate may be maintained in a low oxygen environment.

A semiconductor device has a first RDL substrate with first conductive pillars formed over a first surface of the first RDL substrate. A first electrical component is disposed over the first surface of the first RDL substrate. A hybrid substrate is bonded to the first RDL substrate. An encapsulant is deposited around the hybrid substrate and first RDL substrate with the first conductive pillars and first electrical component embedded within the encapsulant. A second RDL substrate with second conductive pillars formed over the second RDL substrate and second electrical component disposed over the second RDL substrate can be bonded to the hybrid substrate. A second RDL can be formed over a second surface of the first RDL substrate. A third electrical component is disposed over a second surface of the first RDL substrate. A shielding frame is disposed over the third electrical component.

A semiconductor package comprises a base substrate, a first semiconductor chip on the base substrate, a first dam structure which overlaps a corner of the first semiconductor chip from a plan view and is placed on the base substrate and a first fillet layer which is placed vertically between the base substrate and the first semiconductor chip, and vertically between the first dam structure and the first semiconductor chip.

A joined body production method includes subjecting a first electronic component and a second electronic component to thermocompression bonding via a hot-melt adhesive sheet. The hot-melt adhesive sheet includes a binder and solder particles. The binder includes a crystalline polyamide resin having a carboxyl group. A melting point of the solder particles is 30 C. to 0 C. lower than a temperature of the thermocompression bonding. When melt viscosities of the hot-melt adhesive sheet are measured under a condition of a heating rate of 5 C./min., the hot-melt adhesive sheet has a ratio of a melt viscosity at 40 C. lower than the temperature of the thermocompression bonding to a melt viscosity at 20 C. lower than the temperature of the thermocompression bonding of no less than 10.

Provided is a semiconductor package including a plurality of first semiconductor chips respectively including a first semiconductor substrate and a plurality of first through electrodes penetrating the first semiconductor substrate, a second semiconductor chip on the plurality of first semiconductor chips, the second semiconductor chip including a second semiconductor substrate and a plurality of second through electrodes penetrating the second semiconductor substrate, a third semiconductor chip on the second semiconductor chip, the third semiconductor chip including a third semiconductor substrate and a plurality of third through electrodes penetrating the third semiconductor substrate, and a first encapsulation material on the plurality of first semiconductor chips, a planar shape of the second semiconductor chip is greater than a planar shape of each first semiconductor chip of the plurality of first semiconductor chips, and a planar shape of the third semiconductor chip is greater than the planar shape of the second semiconductor chip.

A method for producing an SMD power semiconductor component module includes providing an SMD circuit carrier equipped with contact points and an insulation, and at least one discrete power semiconductor component equipped with electrically conductive connection elements, preferably connection legs. The at least one discrete power semiconductor component, equipped with electrically conductive connection elements, is arranged on the side of the SMD circuit carrier equipped with the contact points. The connection elements of the power semiconductor component contact the contact points of the SMD circuit carrier, and the connection elements are connected to the respectively assigned contact points by laser welding.

A semiconductor package comprises a first die having a central region and a peripheral region that surrounds the central region; a plurality of through electrodes that penetrate the first die; a plurality of first pads at a top surface of the first die and coupled to the through electrodes; a second die on the first die; a plurality of second pads at a bottom surface of the second die, the bottom surface of the second die facing the top surface of the first die; a plurality of connection terminals that connect the first pads to the second pads; and a dielectric layer that fills a space between the first die and the second die and surrounds the connection terminals. A first width of each of the first pads in the central region may be greater than a second width of each of the first pads in the peripheral region.

Various embodiments of the teachings herein include a sintered power electronic module with a first plane and a second plane different from the first plane. An example comprises: a first substrate with a first metallization arranged on the first plane; a second substrate with a second metallization arranged on the second plane; a switchable die having a first power terminal and a second power terminal, the die arranged between the first substrate and the second substrate; and a surface area of all the sintered connections of the first plane is between 90 and 110% of a surface area of all the sintered connections of the second plane. The first power terminal of the die is joined to the first metallization via a sintered connection in the first plane and the second power terminal is joined to the second metallization via a sintered connection in the second plane.

A semiconductor package may include a first semiconductor chip, second semiconductor chips stacked on the first semiconductor chip in a vertical direction, adhesive layers interposed between the first semiconductor chip and one of the second semiconductor chips and between the second semiconductor chips, and a molding member on the first semiconductor chip. Edges of the adhesive layers may be positioned inward from sidewalls of the second semiconductor chips. The molding member may cover at least sidewalls of the second semiconductor chips and sidewalls of the adhesive layers. The molding member may fill edge gaps defined by the sidewalls of the adhesive layers and edges of upper surfaces and lower surfaces of the second semiconductor chips.