A fan-out wafer level packaging (FOWLP) unit which includes a substrate, at least one die, a first dielectric layer, at least one conductive pillar, a second dielectric layer, a plurality of first conductive circuits, a first outer protective layer, a third dielectric layer, a plurality of second conductive circuits, and a second outer protective layer is provided. The die is electrically connected with the outside through at least one first bonding pad around a chip area on a second surface of the die. The die is further electrically connected with the outside through a second bonding pad in at least one opening of the second outer protective layer. Both the first conductive circuits and the second conductive circuits are produced by filling a metal paste into slots and grinding the metal paste. Thereby problems of conventional FOWLP technology including higher manufacturing cost and less environmental benefit can be solved.

A system includes: an inverter configured to convert DC power to AC power, wherein the inverter includes: a power module including: a first substrate, a second substrate including a source plane and a gate plane separated from the source plane by a full trench, the source plane including a step trench, and the gate plane including an electrical connection through the second substrate to a gate input connection of the power module, a semiconductor die disposed between the first substrate and the second substrate, the step trench formed in a portion of the source plane corresponding to an edge of the semiconductor die, and the semiconductor die including a gate connected to the gate plane, and a sinter element disposed between the semiconductor die and the second substrate to connect the semiconductor die to the second substrate; a battery; and a motor.

Suppressing deflection and reducing weight are to be achieved. A supporting glass substrate has a ratio of a Young's modulus (GPa) to a density (g/cm.sup.3) that is 37.0 (GPa.Math.cm.sup.3/g) or more and the ratio has a value larger than a ratio calculation value, the ratio calculation value being a ratio of a Young's modulus (GPa) calculated from a composition to a density (g/cm.sup.3). The ratio calculation value is represented by the following expression: =2.Math.{(V.sub.i.Math.G.sub.i)/M.sub.i.Math.X.sub.i}, where, in the expression, V.sub.i is a filling parameter of a metal oxide contained in the supporting glass substrate, G.sub.i is a dissociation energy of a metal oxide contained in the supporting glass substrate, M.sub.i is a molecular weight of a metal oxide contained in the supporting glass substrate, and X.sub.i is a molar ratio of a metal oxide contained in the supporting glass substrate.

A semiconductor device includes a substrate, a conductive section, a sealing resin, and a conductive section wire. The substrate includes a substrate obverse face and a substrate reverse face oriented in opposite directions to each other in a thickness direction. The conductive section is formed of a conductive material and located on the substrate obverse face. The conductive section includes a first section and a second section spaced apart from each other. The sealing resin covers at least a part of the substrate and an entirety of the conductive section. The conductive section wire is conductively bonded to the first section and the second section of the conductive section.

Manufacturing is facilitated while deflection is suppressed, and transmission ability is increased. A glass (10) contains SiO.sub.2: 40% to 60%, B.sub.2O.sub.3: 0.01% to 15%, and Al.sub.2O.sub.3+rare earth oxide: 0% to 20% as expressed in mol % on an oxide basis, and the ratio of the total content of Al.sub.2O.sub.3 and RO to the total content of SiO.sub.2, Al.sub.2O.sub.3, and RO (that is, (Al.sub.2O.sub.3+RO)/(SiO.sub.2+Al.sub.2O.sub.3+RO)) is 0.38 or more.

A glass substrate for semiconductors includes a first principal surface and a second principal surface disposed to face opposite the first principal surface, in which a wiring layer is to be formed on at least one of the first principal surface and the second principal surface. The glass substrate for semiconductors has a hole formed in at least one of the first principal surface and the second principal surface, and the glass substrate for semiconductors has an identification mark for identifying the glass substrate between the first principal surface and second principal surface. The minimum value of a shortest distance and a shortest distance is equal to or greater than 100 m. A ratio (d1 ave/d2 ave) is 0.03-33. A ratio (d3 ave/d ave) is 0.01-0.50.

Manufacturing can be facilitated while deflection is suppressed. A glass (10) has a Young's modulus of 95 GPa or more, a coefficient of linear thermal expansion of 5.5 ppm/ C. or less, and a devitrification suppression parameter value represented by Formula (1) of 6.0 or more.

The present invention relates to a ceramic substrate and a method for manufacturing the same, the ceramic substrate comprising: a ceramic base material; a first electrode pattern and a second electrode pattern formed on the upper and lower surfaces of the ceramic base material; and a third electrode pattern which is formed on the upper surface of the ceramic base material and is spaced apart from the first electrode pattern, wherein a volume ratio obtained by dividing the total volume of the first electrode pattern by the total volume of the second electrode pattern may be 0.9 to 1.1.

The method of preparing an all-glass stacked packaging structure includes the following steps: S1: providing an embedded chip fan-out packaging structure provided with a glass substrate and a glass metallized circuit structure provided with a glass substrate, and butt-joining and securing by welding a metal bump of the embedded chip fan-out packaging structure to a second redistribution layer of the glass metallized circuit structure; and S2: filling a gap between the embedded chip fan-out packaging structure and the glass metallized circuit structure with an inorganic silicate or an alkali metal-free silicon compound, and carrying out sintering to obtain the all-glass stacked packaging structure.

A vertical interconnect micro-component adapted for radio frequency signal transmission, preferably for the use in three-dimensional integrated circuits, including: a glass substrate with a first side and a second side opposite to the first side, at least one inner through connector formed in the glass substrate, wherein the inner through connector includes an inner cavity in the glass substrate extending from the first side to the second side of the glass substrate, the inner cavity being fully or partially filled with solid conductor material, and an outer through connector structure formed in the glass substrate and surrounding the at least one inner through connector, the outer through connector structure including one or more outer cavities in the glass substrate extending from the first side to the second side of the glass substrate, the one or more outer cavities each being fully or partially filled with solid conductor material.