A glass layer having a first surface and a second surface opposing each other in a first direction; a plurality of conductive through-vias penetrating at least a portion of the glass layer between the first surface and the second surface; and a capacitor member including a plurality of conductive electrodes each penetrating at least a portion of the glass layer between the first surface and the second surface. At least a portion of the plurality of conductive electrodes has regions overlapping each other in a second direction perpendicular to the first direction.

A metallized ceramic substrate and a manufacturing method thereof are provided. The manufacturing method includes providing a ceramic substrate layer; performing a first selective plating operation that forms at least one electrode metal structure protruding on a surface of the ceramic substrate layer based on a first selective plating area defined by a first pattern mask, in which an outer layer of the at least one electrode metal structure away from the ceramic substrate layer is a thin gold layer having a first thickness; and performing a second selective plating operation that forms a thick gold layer on the thin gold layer based on a second selective plating area defined by a second pattern mask, in which the thick gold layer has a second thickness greater than the first thickness.

A manufacturing method of a circuit board structure includes the following steps. A first sub-circuit board having an upper surface and a lower surface opposite to each other and including at least one conductive through hole is provided. A second sub-circuit board including at least one conductive through hole is provided on the upper surface of the first sub-circuit board. A third sub-circuit board including at least one conductive through hole is provided on the lower surface of the first sub-circuit board. The first sub-circuit board, the second sub-circuit board, and the third sub-circuit board are laminated so that at least two of their conductive through holes are alternately arranged in an axial direction perpendicular to an extending direction of the first sub-circuit board. The first sub-circuit board, the second sub-circuit board, and the third sub-circuit board are electrically connected to one another.

A power module includes: a first substrate having an outer surface and an inner surface; a semiconductor die coupled to the inner surface of the first substrate; a second substrate having an outer surface and an inner surface, the semiconductor die being coupled to the inner surface of the second substrate; and a flex circuit coupled to the semiconductor die.

According to the present disclosure, a packaging substrate includes a glass core and an adhesion reinforcement layer disposed on the glass core. The adhesion reinforcement layer includes a first adhesion reinforcement layer and a second adhesion reinforcement layer disposed on the first adhesion reinforcement layer. The first adhesion reinforcement layer includes a transition metal and silicon. The second adhesion reinforcement layer includes a transition metal. In such a case, it is possible to improve the bonding strength of the conductive layer with respect to the glass core, while effectively suppressing damage to the packaging substrate caused by the difference in thermal expansion properties between the glass core and the conductive layer.

A circuit board according to an embodiment includes an insulating layer; and, an electrode part disposed in the insulating layer, wherein the electrode part includes: a first electrode; a second electrode disposed on the first electrode; and first and second via electrodes disposed between the first electrode and the second electrode, the first via electrode is connected to the first electrode and the second electrode, and a length of the second via electrode in a vertical direction is smaller than a length of the first via electrode in the vertical direction.

A package structure is provided. The package structure includes a package substrate, an inorganic substrate over the package substrate, and a package component over the inorganic substrate. The package structure includes a plurality of conductive connectors penetrating the inorganic substrate and electrically connected to the package component and the package substrate. The package structure also includes an underfill formed around the conductive connectors and between the package component and the inorganic substrate.

A device comprises a first substrate directly hybrid bonded to a second substrate. The first substrate comprises at least one first conductive feature on at least one optical device material stack disposed in a first dielectric layer. The second substrate comprises at least one second conductive feature disposed in a second dielectric layer. A thickness of the at least one first conductive feature is less than about 300 nm, and a thickness of the at least one optical device material stack is greater than about 2 microns.

A semiconductor package includes a glass substrate including a glass core and through-vias, an upper redistribution structure including a plurality of upper redistribution layers disposed on the glass substrate and electrically connected to the through-vias, a first chip structure and a second chip structure disposed on the upper redistribution structure and electrically connected to the upper redistribution structure, an encapsulant at least partially covering the first chip structure and the second chip structure, a lower redistribution structure disposed below the glass substrate and including at least one lower redistribution layer electrically connected to the through-vias, and an interconnection chip disposed below the lower redistribution structure and electrically connecting the first chip structure to the second chip structure.

A power module includes a first end power semiconductor element and a second end power semiconductor element. A first sum is a sum of a path length between the gate electrode of the first end power semiconductor element and a first control terminal and a path length between the source electrode of the first end power semiconductor element and a first detection terminal. A second sum is a sum of a path length between the gate electrode of the second end power semiconductor element and the first control terminal and a path length between the source electrode of the second end power semiconductor element and the first detection terminal. The power module includes a first control layer connected to the gate electrode. The first control layer includes a first detour portion that detours the path to reduce a difference between the first sum and the second sum.