Digital microfluidic (DMF) methods and apparatuses (including devices, systems, cartridges, DMF readers, etc.), and in particular DMF apparatuses and methods adapted for large volume. For example, described herein are methods and apparatuses for DMF using an air gap having a width of the gap that may be between 0.3 mm and 3 mm. Also described herein are DMF readers for use with a DMF cartridges, including those adapted for use with large air gap/large volume, although smaller volumes may be used as well.

Backend optical interconnects may be formed in backend of line (BEOL) layers together with conductive interconnects, and may enable high data-rate communication in a dense and cost-effective manner. In one example, backend optical interconnects can be formed using existing structures in the process (e.g., vias and lines). For example, an IC structure may include an interconnect layer over a device region, where the interconnect layer includes both conductive interconnects and optical interconnects (e.g., wave guides). The optical interconnect includes a core material (e.g., a dielectric material) and may be parallel to metal lines or may be a via that is orthogonal to metal lines in the interconnect layer.

There is provided an electronic device including: a connection substrate which is provided with a plurality of capacitor structure portions; an electronic element which is provided above the connection substrate; connection wiring which connects the electronic element to the connection substrate, in which the plurality of capacitor structure portions have at least one connection capacitor portion which is connected to the connection wiring, and at least one non-connection capacitor portion which is not connected to the connection wiring. The non-connection capacitor portion may be a capacitor in a short state or an open state. The connection substrate may be a first semiconductor wafer.

Disclosed are a staircase structure, a method for manufacturing the same, and a semiconductor structure. The staircase structure includes: a plurality of conductive layers spaced apart along a first direction and a plurality of step structures spaced apart along a second direction. Each conductive layer includes at least two sub-conductive layers spaced apart along a second direction, and the conductive layer extends along a third direction. One column of the sub-conductive layers being in contact connection with at least one step structure. Each step structure includes a plurality of conductive pillars electrically insulated from each other. One conductive pillar is in contact connection with one sub-conductive layer, and the conductive pillar in contact connection with the one sub-conductive layer is electrically insulated from the other sub-conductive layers. In a column of the conductive layers, the conductive layers are in contact connection with the conductive pillars in a one-to-one manner.

A reticle-stitched integrated circuit is provided. The reticle-stitched integrated circuit extends over a first die area and a second die area of an integrated circuit wafer. While individually the first die area and the second die area are within their respective reticle limits, collectively the first die area and the second die area exceed the reticle limit. A first layer of the reticle-stitched integrated circuit may have communication wires that remain exclusively in only one of the first die area and the second die area. A second layer of the reticle-stitched integrated circuit may have communication wires that overlap the first die area and the second die area, thereby allowing communication between the two die areas and enabling the reticle-stitched integrated circuit to exceed the limit of the reticle.

A method of forming a back-side power rail device includes forming a device layer over a front-side of a substrate, forming a first interconnect structure over the device layer, the first interconnect structure including a first conductive feature, forming a first dielectric layer over the first interconnect structure, forming a compressive material layer over the first dielectric layer, forming a bonding layer over the first dielectric layer and the compressive material layer, bonding a carrier substrate with the bonding layer, removing, from a back-side of the substrate, at least a portion of the substrate to expose the device layer, forming one or more back-side vias coupled with the device layer opposite the first interconnect structure, forming a second interconnect structure over the device layer and the one or more back-side vias, and forming one or more second conductive features over the second interconnect structure.

In one example, a semiconductor structure or device comprises a substrate comprising a conductive structure having a top side and a first shielding terminal on the top side of the conductive structure, an electronic component on the top side of the conductive structure, a package body on the top side of the conductive structure and contacting a side of the electronic component, a shield on a top side of the package body and a lateral side of the package body, and a shield interconnect coupling the shield to the first shielding terminal of the conductive structure. Other examples and related methods are also disclosed herein.

A wafer stacking process is provided in the present invention, including steps of forming a silicon oxide layer on a sacrificial carrier, bonding the silicon oxide layer with a dielectric layer on a front side of a silicon substrate, performing a thinning process on the back side of the silicon substrate to expose TSVs therewithin, bonding the back side of the silicon substrate with another silicon substrate, repeating the thinning process and the process of bonding another silicon substrate above so as to form a wafer stacking structure, and performing a removing process to completely remove the sacrificial carrier.

A chip includes an active device, a first backside thermally conductive layer, and a second backside thermally conductive layer, wherein the first backside thermally conductive layer is between the active device and the second backside thermally conductive layer. The chip also includes a first via electrically coupled to the active device, wherein the first via extends through the first backside thermally conductive layer, and a first metal path electrically coupled to the first via, wherein the first metal path extends through the second backside thermally conductive layer.

In an embodiment, a method of fabricating a semiconductor chip is provided. The method includes: providing a semiconductor wafer; forming active device structures in component positions with kerf regions located at least one of adjacent to and between the component positions; forming one or more auxiliary structures at least partially in one or more of the kerf regions; forming a metallization structure on the component positions and on the kerf regions; forming one or more auxiliary contact pads in the component positions that are electrically coupled to one or more of the auxiliary structures in the kerf regions; and singulating the wafer by cutting along the kerf regions.