Aspects and embodiments disclosed herein include a semiconductor device comprising a metal-insulator-metal capacitor having a capacitance. The metal-insulator-metal capacitor comprises a plurality of metal-insulator-metal capacitors coupled in parallel, each metal-insulator-metal capacitor of the plurality of metal-insulator-metal capacitors having a top plate, a bottom plate, and a corresponding capacitance, and a plurality of bottom contacts, at least one of the plurality of bottom contacts arranged between a pair of directly adjacent metal-insulator-metal capacitors of the plurality of metal-insulator-metal capacitors. Also disclosed are antennaplexers, electronic device modules, and electronic devices including aspects and embodiments of the semiconductor device.

A semiconductor device is provided including a backside deep trench capacitor present in a deep trench device region and electrically connected to a source/drain region of a transistor and to a backside back-end-of-the-line (BEOL) structure. In some embodiments, the semiconductor device can also include a logic device region including at least one logic transistor that is located adjacent to the deep trench device region.

This disclosure relates to embodiments that include an apparatus that may comprise a first layer including a first plurality of active devices, a second layer including a second plurality of active devices, and/or a third layer including a plurality of passive devices and disposed between the first and the second layers. An active device of the first plurality of active devices and an active device of the second plurality of active devices may influence a state of charge of a passive device of the plurality of passive devices.

A package substrate is disclosed. The package substrate includes a die package in the package substrate located at least partially underneath a location of a power delivery interface in a die that is coupled to the surface of the package substrate. Connection terminals are accessible on a surface of the die package to provide connection to the die that is coupled to the surface of the package substrate. Metal-insulator-metal layers inside the die package are coupled to the connection terminals.

A semiconductor device capable of suppressing an increase in chip area due to the widening of a conductor located on the topmost layer of a sealing ring is provided. The semiconductor device includes a semiconductor substrate and the sealing ring. The sealing ring is formed on a periphery of the semiconductor substrate in a plan view. The sealing ring includes a plurality of conductors stacked on each other. Each of the plurality of conductors has an inner peripheral edge and an outer peripheral edge. An inner peripheral edge of a first conductor, which is located on the topmost layer of the plurality of conductors, is positioned more inward than any of inner peripheral edges of a plurality of second conductors located below the first conductor in a plan view.

Electronic device including a primary capacitor extending on a semiconductor body accommodating a floating P-well and an N-type buried layer, to provide a P-N junction. This structure introduces a junction capacitance in series with the parasitic capacitance that the primary capacitor forms with the semiconductor body, effectively lowering the overall parasitic capacitance of the electronic device.

An integrated circuit device, having a first number of terminals, and a first plurality of functional circuits including a second number of functional circuits requiring access to the terminals in the first number of terminals, where the second number is greater than the first number, includes a second plurality of functional circuits from among the first plurality of functional circuits, the second plurality of functional circuits sharing access to a shared terminal among the first number of terminals, and a respective isolation circuit between the shared terminal among the first number of terminals and each respective functional circuit in the second plurality of functional circuits, the respective isolation circuit being configured to prevent coupling of noise from one respective functional circuit in the second plurality of functional circuits to another respective functional circuit in the second plurality of functional circuits via the shared terminal.

An image sensor device includes a capacitor structure that is configured to store charge associated with a photocurrent that is generated by a pixel sensor in a pixel sensor array of the image sensor device. The capacitor structure may include bottom electrode layers and top electrode layers that are arranged in an alternating manner and separated by insulator layers. The ends of the bottom electrode layers facing a top contact structure are etched such that the ends of the bottom electrode layers are spaced apart from the top contact structure. Similarly, the ends of the top electrode layers facing a bottom contact structure are etched such that the ends of the top electrode layers are spaced apart from the bottom contact structure.

A metal-insulator-metal capacitor (MIMCAP) structure of a semiconductor device is provided. The MIMCAP structure includes a substrate, first and second contacts formed at opposite sides of the substrate to define a MIMCAP region between the first and second contacts, vertical mandrels extending vertically upwardly from an uppermost surface of the substrate within the MIMCAP region and a MIMCAP. The MIMCAP is disposed in operable contact with the first and second contacts, on exposed sections of the uppermost surface of the substrate and over and around the vertical mandrels within the MIMCAP region. The MIMCAP includes horizontal sections between and over the vertical mandrels and outside outermost ones of the vertical mandrels and vertical sections along respective sidewalls of each of the vertical mandrels.

A semiconductor device including a capacitive HV isolation component and a method of fabrication thereof is disclosed. In one example, the semiconductor device comprises a semiconductor substrate, a bottom capacitor plate over the semiconductor substrate, a top capacitor plate over the bottom capacitor plate, and one or more conductive posts extending between the bottom plate and the top plate.