H10W20/4473

Power module

A power module (10) includes a power semiconductor chip (1) and a Cu circuit (3) having the power semiconductor chip (1) provided on one surface. The power module (10) includes: a sintering layer (2) joining the power semiconductor chip (1) and the Cu circuit (3) by using a sintering paste; and a heat dissipation sheet (4) provided for joining a Cu base plate (5) to the other surface of the Cu circuit (3), in which in a first laminated structure in which the power semiconductor chip (1), the sintering layer (2), the Cu circuit (3), and the heat dissipation sheet (4) are laminated, the total thermal resistance XA in the direction of lamination is equal to or less than 0.30 (K/W).

SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF

A semiconductor structure and a manufacturing method thereof are provided. The manufacturing method of the semiconductor structure includes: forming a sacrificial layer in a concave in a metal layer; recessing the sacrificial layer; filling a metal-organic framework layer in the concave; and removing the sacrificial layer to form an air gap in the concave.

SEMICONDUCTOR DEVICE INCLUDING INTERCONNECT STRUCTURE AND METHOD FOR MANUFACTURING THE SAME

A method for manufacturing a semiconductor device includes: forming an adhesion layer on an interconnect structure disposed over a substrate; forming a plurality of conductive interconnects on the adhesion layer, the plurality of conductive interconnects being spaced apart from each other so as to form a plurality of trenches among the plurality of conductive interconnects and to expose a plurality of portions of the adhesion layer through the plurality of trenches, respectively; and forming the plurality of portions of the adhesion layer into a molecular organic framework layer such that the molecular organic framework layer fills the plurality of trenches.

Fill of vias in single and dual damascene structures using self-assembled monolayer

Metallization interconnect structures, integrated circuit devices, and methods related to high aspect ratio interconnects are discussed. A self assembled monolayer is selectively formed on interlayer dielectric sidewalls of an opening that exposes an underlying metallization structure. A first metal is formed on the underlying metallization structure and within only a bottom portion of the self assembled monolayer. The exposed portion of the self assembled monolayer is removed and a second metal is formed over the first metal.