A power semiconductor module includes a power semiconductor element having a first electrode, a second electrode, and a control electrode. The power semiconductor element is configured to selectively control a conductivity state between the first electrode and the second electrode. The power semiconductor module further includes a first power line electrically connected to the first electrode, a second power line electrically connected to the second electrode, a first control line electrically connected to the control electrode, a second control line electrically connected to the second electrode, and a heat sink having a front surface on which the power semiconductor element is formed. The heat sink includes a shielding layer. The first control line and the second control line extend through the heat sink.

A semiconductor device includes a package body having a topside in a first plane and a bottom side in a second plane parallel to the first plane. At least one lead protruding out of the package body has a first portion in a plane parallel to the first plane and a second portion being bent away from the first plane towards the second plane. A cavity is positioned between the at least one lead and a feature of the semiconductor device. A removable dielectric spacer is configured to be positioned in the cavity between the at least one lead and the feature. The dielectric spacer is longer than the at least one lead.

A system comprises: an inverter configured to convert DC power from a battery to AC power to drive a motor, wherein the inverter includes: a power switch including a drain terminal, a source terminal, and a gate terminal; and a controller configured to detect a change in current at the source terminal of the power switch using a complex impedance of a metal trace connected to the source terminal of the power switch, and control a gate control signal to the gate terminal based on the detected change in current.

A semiconductor packaging device includes a packaging module, a heat dissipation cover and a thermal interface material layer. The package module includes a substrate, and a working chip mounted on the substrate. The heat dissipation cover includes a metal cover fixed on the substrate and covering the working chip, an accommodating recess located on the metal cover to accommodate the working chip, and a plurality of protrusive columns respectively formed on the metal cover and distributed within the accommodating recess at intervals. The depth of the accommodating recess is greater than the height of each protrusive column, and the accommodating recess is greater than the working chip. The thermal interface material layer is non-solid, and located within the accommodating recess between the protrusive columns to wrap the protrusive columns and contact with the working chip, the metal cover and the protrusive columns.

A semiconductor device includes a first redistribution structure, a first semiconductor package, a second semiconductor package, an encapsulation layer, a first thermal interface material (TIM) layer, and a second TIM layer. The first semiconductor package and the second semiconductor package are respectively disposed on the first redistribution structure and laterally disposed aside with each other. The encapsulation layer encapsulates and surrounds the first semiconductor package and the second semiconductor package. The first semiconductor package and the second semiconductor package are respectively exposed from the encapsulation layer. The first TIM layer and the second TIM layer are respectively disposed on back surfaces of the first semiconductor package and the second semiconductor package. A top surface of the first TIM layer and a top surface of the second TIM layer are coplanar with a top surface of the encapsulation layer.

A semiconductor package assembly and an electronic device are provided. The semiconductor package assembly includes a base, a system-on-chip (SOC) package, a memory package and a silicon capacitor die. The base has a first surface and a second surface opposite the first surface. The SOC package is disposed on the first surface of the base and includes a SOC die having pads and a redistribution layer (RDL) structure. The RDL structure is electrically connected to the SOC die by the pads. The memory package is stacked on the SOC package and includes a memory package substrate and a memory die. The memory package substrate has a top surface and a bottom surface. The memory die is electrically connected to the memory package substrate. The silicon capacitor die is disposed on and electrically connected to the second surface of the base.

A module arrangement for power semiconductor devices, includes two or more heat spreading layers with a first surface and a second surface being arranged opposite to the first surface. At least two or more power semiconductor devices are arranged on the first surface of the heat spreading layer and electrically connected thereto. An electrical isolation stack comprising an electrically insulating layer and electrically conductive layers is arranged in contact with the second surface of each heat spreading layer. The at least two or more power semiconductor devices, the heat spreading layers and a substantial part of each of the electrical isolation stacks are sealed from their surrounding environment by a molded enclosure. Accordingly, similar or better thermal characteristic of the module can be achieved instead of utilizing high cost electrically insulating layers, and double side cooling configurations can be easily implemented, without the use of a thick baseplate.

A semiconductor package includes a redistribution substrate, a chip stack structure disposed on the redistribution substrate and including a plurality of semiconductor chips disposed in a stack, a vertical wiring portion connecting the chip stack structure to the redistribution substrate and including a plurality of vertical wires that extend in a direction perpendicular to an upper surface of the redistribution substrate, a sealing member configured to seal at least a portion the chip stack structure and the vertical wiring portion, and a heat dissipation metal member disposed on side surfaces and an upper surface of the sealing member.

The present disclosure relates to a flip-chip based moisture-resistant module, which includes a substrate with a top surface, a flip-chip die, a sheet-mold film, and a barrier layer. The flip-chip die has a die body and a number of interconnects, each of which extends outward from a bottom surface of the die body and is attached to the top surface of the substrate. The sheet-mold film directly encapsulates sides of the die body, extends towards the top surface of the substrate, and directly adheres to the top surface of the substrate, such that an air-cavity with a perimeter defined by the sheet-mold film is formed between the bottom surface of the die body and the top surface of the substrate. The barrier layer is formed directly over the sheet-mold film, fully covers the sides of the die body, and extends horizontally beyond the flip-chip die.

Provided is an electronic device having further excellent operation reliability. An electronic device according to an embodiment of the present disclosure includes a first device board, a second device board, and a hollow. The second device board is stacked on the first device board and electrically coupled to the first device board, and has an area larger than an area of the first device board. The hollow surrounds, along a plane orthogonal to a stacking direction of the first device board and the second device board, at least a portion of a periphery of the first device board.