Described herein are integrated circuit (IC) structures, devices, and methods associated with device layer interconnects. For example, an IC die may include a device layer including a transistor array along a semiconductor fin, and a device layer interconnect in the transistor array, wherein the device layer interconnect is in electrical contact with multiple different source/drain regions of the transistor array.

In one example, an electronic device comprises a substrate comprising a conductive structure and a dielectric structure, the dielectric structure comprising an upper dielectric layer, an electronic component over a top side of the substrate and coupled with the conductive structure, an encapsulant over the top side of the substrate and adjacent a lateral side of the electronic component, and a shield over the top side of the electronic component and contacting a lateral side of the encapsulant and a first lateral side of the substrate. The conductive structure comprises a first tab structure at the first lateral side of the substrate, and wherein the first tab structure contacts the shield and extends above the upper dielectric layer. Other examples and related methods are also disclosed herein.

A method of manufacturing a semiconductor package of stacked semiconductor chips includes forming a reverse wire bond by bonding one end of a reverse wire to a chip pad of the second-highest semiconductor chip of the stacked semiconductor chips and connecting the other end of the reverse wire to a conductive bump on a chip pad of the uppermost semiconductor chip of the stacked semiconductor chips. The method also includes molding the stacked semiconductor chips with the reverse wire bond using a mold layer. The method further includes processing the mold layer to expose the conductive bump and the other end of the reverse wire in the reverse wire bond through an upper surface of the mold layer.

A semiconductor package includes a first redistribution substrate, a passive device mounted on a bottom surface of the first redistribution substrate, a first semiconductor chip disposed on a top surface of the first redistribution substrate, the first semiconductor chip including a through via disposed therein, a second semiconductor chip disposed on the first semiconductor chip, and a conductive post disposed between the top surface of the first redistribution substrate and a bottom surface of the second semiconductor chip and spaced apart from the first semiconductor chip. The conductive post is connected to the first redistribution substrate and to the second semiconductor chip. The conductive post overlaps with at least a portion of the passive device in a vertical direction normal to the top surface of the first redistribution substrate.

A method of forming a wafer-level package includes singulating a wafer into a plurality of reconstituted integrated circuit dies, affixing a carrier to a front side of the plurality of integrated circuit dies, and forming a laser direct structuring (LDS) activatable resin over a back side of the plurality of integrated circuit dies, over side edges of the plurality of integrated circuit die, and over adjacent portions of the carrier. Desired areas of the LDS activatable resin are activated to form conductive areas within the LDS activatable resin, at least one of the conductive areas associated with each integrated circuit die being formed to contact a respective pad of that integrated circuit die and to run alongside to and in contact with a side of the LDS activatable resin in contact with a side edge of that integrated circuit die.

A package structure and a method of forming the same are provided. The package structure includes a first die, a second die, a first encapsulant, and a buffer layer. The first die and the second die are disposed side by side. The first encapsulant encapsulates the first die and the second die. The second die includes a die stack encapsulated by a second encapsulant encapsulating a die stack. The buffer layer is disposed between the first encapsulant and the second encapsulant and covers at least a sidewall of the second die and disposed between the first encapsulant and the second encapsulant. The buffer layer has a Young's modulus less than a Young's modulus of the first encapsulant and a Young's modulus of the second encapsulant.

A method of manufacturing a semiconductor package may include disposing, in a lower mold, a substrate strip in which a plurality of semiconductor chips are arranged in a horizontal direction, providing, in an upper mold, a release film to which a first encapsulant is attached, allowing the upper mold and the lower mold to be proximate to each other such that a first encapsulant is adjacent to an upper surface of each of the plurality of semiconductor chips, injecting a second encapsulant into a space between the upper mold and the lower mold, heating the first encapsulant and the second encapsulant to form a molded structure including a first encapsulating layer and a second encapsulating layer, allowing the upper mold and the lower mold to be spaced from each other such that the molded structure is separated from the release film, and cutting the molded structure.

A semiconductor package includes a redistribution structure including redistribution patterns, first and second chip structures on the redistribution structure and electrically connected to the redistribution patterns, a first mold covering at least a portion of each of the first and second chip structures, an interconnection chip including interconnection patterns electrically connected to the redistribution patterns and a plurality of insulating layers having third surfaces in which respective ones of the interconnection patterns are embedded, through-vias electrically connected to the redistribution patterns, a second mold covering at least a portion of each of the through-vias and the interconnection chip. Each third surface includes a first region, and a second region between the first region and an upper surface of the respective interconnection pattern embedded in the third surface. The second region defines a step between the first region and the upper surface of the interconnection pattern embedded in the third surface.

A semiconductor package includes a redistribution structure, a first semiconductor chip above the redistribution structure, a second semiconductor chip on, and offset relative to, the first semiconductor chip, a plurality of first conductive posts extending from a bottom surface of the second semiconductor chip to a top surface of the redistribution structure, a third semiconductor chip on the second semiconductor chip, a plurality of second conductive posts extending from a bottom surface of the third semiconductor chip to the top surface of the redistribution structure, and a molding layer between the top surface of the redistribution structure and the bottom surface of the third semiconductor chip.

A semiconductor package includes: a substrate; four semiconductor chips spaced apart from each other on the substrate, each of the four semiconductor chips including an active surface that is perpendicular to an upper surface of the substrate; wires extending from the active surface of each of the four semiconductor chips, respectively, and electrically connecting the four semiconductor chips and the substrate; and an encapsulant on the substrate and surrounding the four semiconductor chips, wherein upper surfaces and first side surfaces of each of the four semiconductor chips are exposed from the encapsulant.