Compositions for increasing material removal rate during CMP polishing and related methods are provided. The composition comprises an oxidizer. The composition comprises a plurality of particles. The composition comprises 0.01% to 5% by weight of at least one rare earth metal salt compound based on a total weight of the composition. When the composition is applied to a silicon carbide substrate and when the silicon carbide substrate is polished, the at least one rare earth metal salt compound is present in an amount sufficient to result in an increase in a material removal rate relative to a control composition. The control composition does not comprise the at least one rare earth metal salt compound.

Embodiments of the present disclosure provide a method and apparatus for polishing a substrate including pre-heating the polishing slurry in-situ. Particularly, the polishing slurry is preheated by a heating element attached to the retaining ring or by rotating the retaining ring relative to the substrate being processed. Pre-heating the slurry on the polishing pad improves polishing uniformity across the substrate by preventing the edge of the substrate being inadvertently cooled by the fresh slurry. Embodiments of the present disclosure further include a retaining ring with a tapered slurry channel, which reduces the decrease of flow area as the retaining ring worn down.

Examples are disclosed that relate to planarizing substrates without use of an abrasive. One example provides a method of chemically planarizing a substrate, the method comprising introducing an abrasive-free planarization solution onto a porous pad, contacting the substrate with the porous pad while moving the porous pad and substrate relative to one another such that higher portions of the substrate contact the porous pad and lower portions of the substrate do not contact the porous pad, and removing material from the higher portions of the substrate via contact with the porous pad to reduce a height of the higher portions of the substrate relative to the lower portions of the substrate. In some examples, linear motion may be used for chemically planarizing.

A method of processing a substrate includes disposing a substrate in a substrate processing apparatus and polishing the substrate. The substrate processing apparatus includes a polishing head and a polishing part. The polishing head includes a polishing head body. The polishing head body includes a pressure member including a first zone and a second zone. The substrate includes a first substrate zone located under the first zone and a second substrate zone located under the second zone. The polishing of the substrate includes rotating the substrate while applying a (1,1)-th pressure to the first substrate zone and applying a (2,1)-th pressure to the second substrate zone, calculating a (1,1)-th polishing rate of the first substrate zone and a (2,1)-th polishing rate of the second substrate zone, determining a reference polishing rate, and resetting a pressure applied to the first substrate zone to a (1,2)-th pressure.

Provided is a means capable of polishing an organic material at a high polishing speed and reducing the number of scratches after polishing. The polishing composition of the present invention contains zirconia particles and a dispersing medium, in which the zirconia particles contain at least one of tetragonal zirconia and cubic zirconia, and an average secondary particle size of the zirconia particles is less than 80 nm.

Systems and methods for grinding semiconductor workpieces are provided. In one example, a method includes providing a surface of the semiconductor workpiece against a grinding apparatus. The grinding apparatus includes an abrasive surface. The method further includes imparting relative motion between the abrasive surface and the semiconductor workpiece to implement a grinding operation on the semiconductor workpiece. The method further includes providing a fluid to the surface of the semiconductor workpiece or the abrasive surface during the grinding operation. The fluid includes an additive. The additive includes one or more of an oxidizing agent, an etchant, a surfactant, or a lubricant.

Provided is a polishing composition for polishing semiconductor wafer surfaces, including a surface-modified monocrystalline diamond with a D(50) particle size ranging from about 0.10 m to about 1 m; a vehicle selected from the group consisting of water-based vehicles, glycol-based vehicles, oil-based vehicles, and hydrocarbon-based vehicles; and optionally one or more additives. Further presented are associated methods for polishing semiconductor wafer surfaces.

A thin film transistor is provided, including a source conductive layer and a drain conductive layer spaced apart from each other; an active layer disposed between the source conductive layer and the drain conductive layer; and a gate electrode overlapping the active layer. A direction from the drain conductive layer to the source conductive layer is referred to as a first direction, and a direction perpendicular to the first direction is referred to as a second direction. The active layer is disposed to stand in a direction that is not parallel to the first direction or the second direction, such that a maximum length of the active layer in the second direction is greater than a minimum length of the active layer in the first direction. This configuration enables a short channel structure while allowing area reduction and maintaining electrical reliability.

Gate-all-around integrated circuit structures having vertically discrete source or drain structures, and methods of fabricating gate-all-around integrated circuit structures having vertically discrete source or drain structures, are described. For example, an integrated circuit structure includes a vertical arrangement of horizontal nanowires. A gate stack is around the vertical arrangement of horizontal nanowires. A first epitaxial source or drain structure is at a first end of the vertical arrangement of horizontal nanowires, the first epitaxial source or drain structure including vertically discrete portions aligned with the vertical arrangement of horizontal nanowires. A second epitaxial source or drain structure is at a first end of the vertical arrangement of horizontal nanowires, the second epitaxial source or drain structure including vertically discrete portions aligned with the vertical arrangement of horizontal nanowires.

A semiconductor device includes a substrate. The semiconductor device further includes a gate structure extending along a first direction. The semiconductor device further includes a first source/drain (S/D) region. The semiconductor device further includes a second S/D region separated from the first S/D region in the first direction. The semiconductor device further includes a backside via extending through the substrate, wherein the backside via is between the first S/D region and the second S/D region. The semiconductor device further includes a silicide layer between a sidewall of the first S/D region and the backside via, wherein the backside via contacts the silicide layer. The semiconductor device further includes a first dielectric spacer between the backside via and the second S/D region, wherein the backside via contacts the first dielectric spacer.