A semiconductor structure and method of forming the same are provided. The semiconductor structure has a conductive structure. The semiconductor structure includes a first conductive line, a second conductive line, a third conductive line and a conductive via. The first conductive line and the second conductive line are located in a first dielectric layer and extend along a first direction. The first conductive line and the second conductive line are spaced from each other by the first dielectric layer therebetween. The third conductive line is located in a second dielectric layer and extends along a second direction. The conductive via is vertically between the first conductive line and the third conductive line, and between the second conductive line and the third conductive line. The conductive via, in a vertical direction, is overlapped with a portion of the first dielectric layer that is laterally between the first conductive line and the second conductive line.

A method of forming a semiconductor structure includes forming a semiconductor device over a substrate, forming a combination of a connection-level dielectric layer and a connection-level metal interconnect structure over the semiconductor device, where the connection-level metal interconnect structure is electrically connected to a node of the semiconductor device and is embedded in the connection-level dielectric layer, forming a line-and-via-level dielectric layer over the connection-level dielectric layer, forming an integrated line-and-via cavity through the line-and-via-level dielectric layer over the connection-level metal interconnect structure, selectively growing a conductive via structure containing cobalt from a bottom of the via portion of the integrated line-and-via cavity without completely filling a line portion of the integrated line-and-via cavity, and forming a copper-based conductive line structure that contains copper at an atomic percentage that is greater than 90% in the line portion of the integrated line-and-via cavity on the conductive via structure.

Embodiments of the disclosure include apparatus and methods for molybdenum nucleation layer formation. A molybdenum nucleation layer is formed on a metal layer disposed within a damascene structure formed in a surface of a substrate maintained at a processing temperature of less than 425 degrees Celsius. The damascene structure includes a plurality of vias and the metal layer is disposed at a bottom surface of the plurality of vias. To form the molybdenum nucleation layer, a molybdenum-containing precursor (MCP) is delivered to the substrate for a first period of time. A reactive precursor gas is delivered to the substrate for the first period of time. A carrier gas is delivered to the substrate for a second period of time. The reactive precursor gas is delivered to the substrate for a third period of time. A molybdenum layer is deposited within the plurality of vias on the molybdenum nucleation layer.

Gate contact structures disposed over active portions of gates and methods of forming such gate contact structures are described. For example, a semiconductor structure includes a substrate having an active region and an isolation region. A gate structure has a portion disposed above the active region and a portion disposed above the isolation region of the substrate. Source and drain regions are disposed in the active region of the substrate, on either side of the portion of the gate structure disposed above the active region. A gate contact structure is disposed on the portion of the gate structure disposed above the active region of the substrate.

A method includes obtaining a base structure including a stack of dielectric layers disposed on a substrate. The stack of dielectric layers includes a first photosensitive dielectric layer including a first photosensitive dielectric material sensitive to a first radiation dose, a second photosensitive dielectric layer including a second photosensitive dielectric material sensitive to a second radiation dose different from the first radiation dose, and a barrier layer disposed between the first photosensitive dielectric layer and the second photosensitive dielectric layer. The method further includes forming a dual damascene structure from the base structure using a dual damascene process.

A manufacturing method of a semiconductor structure includes forming a first interconnect structure over a first semiconductor substrate; forming a through substrate via (TSV) to penetrate through the first semiconductor substrate and extend into the first interconnect structure, where the TSV includes a first surface in the first interconnect structure and a second surface opposite to the first surface; and forming a first bonding conductor on the first interconnect structure to be electrically coupled to the TSV through the first interconnect structure, where the first bonding conductor includes a first bonding surface facing away the first interconnect structure, and a boundary of the first bonding surface of the first bonding conductor overlaps a boundary of the first surface of the TSV.

The present application discloses a semiconductor device with a composite barrier structure and a method for fabricating the semiconductor device. The semiconductor device includes a substrate; a first dielectric layer having a feature opening on a substrate; a composite barrier structure in the feature opening, wherein the composite barrier structure includes a barrier layer in the feature opening and an assisting blocking layer on the barrier layer; and a conductive feature on the assisting blocking layer; wherein the barrier layer comprises tantalum, and the assisting blocking layer comprises copper manganese alloy.

A wet etching chemistry to selectively remove a polymer residue on an opening embedded in a low-k dielectric layer and an underlying stop layer in a process of forming an interconnect structure is provided. The wet etching chemistry includes: two type of organic solvents, wherein a concentration of the two type of organic solvents is greater than or equal to 70%; an Alkali source amine, at least comprising a tertiary amine; an inhibitor; and water. In some embodiment, the wet etching chemistry is free of a peroxide to avoid damage to the WdC hard mask.

Implementations of low-resistance copper interconnects and manufacturing techniques for forming the low-resistance copper interconnects described herein may achieve low contact resistance and low sheet resistance by decreasing tantalum nitride (TaN) liner/film thickness (or eliminating the use of tantalum nitride as a copper diffusion barrier) and using ruthenium (Ru) and/or zinc silicon oxide (ZnSiO.sub.x) as a copper diffusion barrier, among other examples. The low contact resistance and low sheet resistance of the copper interconnects described herein may increase the electrical performance of an electronic device including such copper interconnects by decreasing the resistance/capacitance (RC) time constants of the electronic device and increasing signal propagation speeds across the electronic device, among other examples.

An apparatus comprises a first metal feature in a first dielectric layer over a substrate, wherein a sidewall portion of the first dielectric layer is over a top surface of the first metal feature, a second dielectric layer over the first dielectric layer and a second metal feature extending through the second dielectric layer, wherein a bottom of a first portion of the second metal feature is in contact with the top surface of the first metal feature and a bottom of a second portion of the second metal feature is in contact with the sidewall portion of the first dielectric layer.