Methods of removing molybdenum oxide from a surface of a substrate comprise exposing the substrate having a molybdenum oxide layer on the substrate to a halide etchant having the formula R.sub.mSiX.sub.4-m, wherein m is an integer from 1 to 3, X is selected from iodine (I) and bromine (Br) and R is selected from the group consisting of a methyl group, ethyl group, propyl group, butyl group, cyclohexyl group and cyclopentyl group. The methods may be performed in a back-end-of-the line (BEOL) process, and the substrate contains a low-k dielectric material.

An excellent method of manufacturing a patterned substrate which is capable of easily patterning an insulation layer to provide a patterned substrate even when a difficult-to-etch material is used for the insulation layer, a patterned substrate obtained thereby, and a patterned substrate intermediate thereof are provided. The method of manufacturing a patterned substrate with the insulation layer and an electrode layer stacked in this order on a substrate comprising: forming an organic resist material layer; irradiating the organic resist material layer with radiation or an electromagnetic wave of a wavelength of 10 to 780 nm and developing the organic resist material layer to form a first patterning layer; and removing the first patterning layer.

Methods and apparatus for etching a wafer. The wafer is positioned adjacent to a cathode within a vacuum chamber. The wafer includes a first layer stack, where the first layer stack includes a crystalline composition of a first element and a second element different from the first element. The crystalline composition may be BaTiO.sub.3 (BTO). A gas is received that includes a first partial gas and a second partial gas. The first and second partial gases may be HBr and Cl.sub.2, respectively. The gas is ionized, and the wafer is chemically etched by bombarding the layer stack with the ionized gas. The chemical etching includes reacting the first partial gas with the first element and reacting the second partial gas with the second element.

A nanowire device includes one or more nanowire having a first end portion, a second end portion, and a body portion between the first end portion and the second end portion. A first conductive structure is in contact with the first end portion and a second conductive structure is in contact with the second end portion. The body portion of the nanowire has a first cross-sectional shape and the first end portion has a second cross-sectional shape different from the first cross-sectional shape. Integrated circuits including the nanowire device and a method of cleaning a semiconductor structure are also disclosed.

A composition for forming a protective film using a polymer having an imide group: cured under a film-forming condition in air and an inert gas; forming a protective film having excellent heat resistance, embedding and planarization ability for a pattern formed on a substrate, and good adhesiveness to the substrate; and forming a protective film having excellent resistance against an alkaline aqueous hydrogen peroxide. A composition for forming a protective film against alkaline aqueous hydrogen peroxide, including: (A) a polymer having a repeating unit represented by general formula (1A) having at least one or more fluorine atoms and at least one or more hydroxy groups, a terminal group is any one of the following general formulae (1B) and (1C); and organic solvent, wherein R.sub.1 represents any one group represented by the following formula (1D), and two or more kinds of R.sub.1 are optionally used in combination. ##STR00001##

Exemplary semiconductor processing methods may include flowing an etchant precursor into a processing region of a semiconductor processing chamber. A substrate may be housed within the processing region. The substrate may define an exposed region of a metal-containing hardmask material and an exposed region of a material characterized by a dielectric constant of less than or about 4.0. The methods may include contacting the substrate with the etchant precursor. The methods may include removing at least a portion of the metal-containing hardmask material.

Disclosed are apparatuses and methods for performing atomic layer etching. A method may include supporting and thermally floating a substrate in a processing chamber, modifying one or more surface layers of material on the substrate by chemical adsorption, without using a plasma, while the substrate is maintained at a first temperature, and removing the one or more modified surface layers by desorption, without using a plasma, while the substrate is maintained at a second temperature, the first temperature being different than the second temperature. An apparatus may include a processing chamber and support features configured to support and thermally float a substrate in the chamber, a process gas unit configured to flow a first process gas onto the substrate, a substrate heating unit configured to heat the substrate, and a substrate cooling unit configured to actively cool the substrate.

Provided is a semiconductor structure, a test structure, a manufacturing method and a test method. The semiconductor structure includes a substrate, which includes multiple pillars spaced along a first direction by first trenches; second trenches formed at opposite sides along a second direction of each of the pillars; target conductive structures extending along the second direction in the substrate directly below adjacent second trenches; and a first dielectric layer, a conductive layer and a second dielectric layer sequentially stacked in the first trenches and the second trenches. A depth of the first trenches is greater than that of the second trenches. The first direction intersects the second direction.

Methods and apparatuses for processing semiconductor substrates in an integration scheme to form chamferless vias are provided herein. Methods include bifurcating etching of dielectric by depositing a conformal removable sealant layer having properties for selective removal relative to dielectric material without damaging dielectric material. Some methods include forming an ashable conformal sealant layer. Methods also include forming hard masks including a Group IV metal and removing conformal removable sealant layers and hard masks in one operation using same etching chemistries.

Selective gas etching for self-aligned pattern transfer uses a first block and a separate second block formed in a sacrificial layer to transfer critical dimensions to a desired final layer using a selective gas etching process. The first block is a first hardmask material that can be plasma etched using a first gas, and the second block is a second hardmask material that can be plasma etched using a second gas separate from the first gas. The first hardmask material is not plasma etched using the second gas, and the second hardmask material is not plasma etched using the first gas.