H10P50/244

Structure manufacturing method and structure
12518974 · 2026-01-06 · ·

A structure is manufactured by forming a mask that has an opening pattern on a fine recessed and projected structure of a substrate having the fine recessed and projected structure with an average period of 1 m or less on a surface thereof, etching the surface of the substrate from a side of the mask to form a recessed portion which has an opening greater than the average period of the fine recessed and projected structure according to the opening pattern of the mask, the recessed portion having a depth equal to or greater than double a difference in height between recesses and projections of the fine recessed and projected structure, and then removing the mask.

THROUGH SUBSTRATE VIA AND FORMING METHOD THEREOF

The present disclosure relates to a method, which includes forming a patterned mask layer having an opening disposed on a first surface of a substrate; performing a cyclic etching and deposition processes from the first surface to form a recess corresponding to the opening and a liner layer disposed thereon; performing a first removal process to remove the liner layer for exposing a portion of the substrate in the recess; and performing a trimming process to remove the portion of the substrate in the recess.

Semiconductor device and method of forming charge balanced power MOSFET combining field plate and super-junction

A semiconductor device has a substrate and semiconductor layer formed over the substrate. A trench is formed through the semiconductor layer. A polysilicon material is disposed in the trench. A first column of semiconductor material having a first conductivity type extends through the semiconductor layer adjacent to the trench. A second column of semiconductor material having a second conductivity type extends through the semiconductor layer adjacent to the first column of semiconductor material. A conductive layer is formed over the semiconductor layer. The polysilicon material is coupled to the conductive layer and operates as a field plate. A first insulating layer is formed between the polysilicon material and a side surface of the trench. A source region is formed within the semiconductor layer. A gate region is formed adjacent to the insulating layer. A second insulating layer is formed between the gate region and source region.

Densification and reduction of selectively deposited Si protective layer for mask selectivity improvement in HAR etching
12563990 · 2026-02-24 · ·

Methods for the fabrication of semiconductor devices are disclosed. A method may include depositing a mask layer on a substrate, forming a protection layer on the mask layer, and modifying the protection layer such that a porosity of the protection layer is reduced. Modifying the protection layer may include densifying the protection layer. Modifying the protection layer may include reducing the protection layer using a hydrogen plasma. The method may include etching the protection layer and the substrate. Etching may include etching, forming the protection layer, and modifying the protection layer in a predetermined number of cycles.

SEMICONDUCTOR PACKAGE ELECTRICAL CONTACT STRUCTURES AND RELATED METHODS

Implementations of a semiconductor package may include a die; a first pad and a second pad, the first pad and the second pad each including a first layer and a second layer where the second layer may be thicker than the first layer. At least a first conductor may be directly coupled to the second layer of the first pad; at least a second conductor may be directly coupled to the second layer of the second pad; and an organic material may cover at least the first side of the die. The at least first conductor and the at least second conductor extend through openings in the organic material where a spacing between the at least first conductor and the at least second conductor may be wider than a spacing between the second layer of the first pad and the second layer of the second pad.

Microelectronic devices including high aspect ratio features

Methods of forming high aspect ratio openings. The method comprises removing a portion of a dielectric material at a temperature less than about 0 C. to form at least one opening in the dielectric material. The at least one opening comprises an aspect ratio of greater than about 30:1. A protective material is formed in the at least one opening and on sidewalls of the dielectric material at a temperature less than about 0 C. Methods of forming high aspect ratio features are also disclosed, as are semiconductor devices.

Substrate processing method, method of manufacturing semiconductor device, substrate processing apparatus, and recording medium
12581882 · 2026-03-17 · ·

There is provided a technique that includes forming a modified film by supplying a modifying gas to modify an unmasked deposited film on a substrate; and removing the modified film, including supplying a removal gas activated by plasma and supplying a protective-film-forming gas at least at the same time.