As an example, the present invention relates to a hybrid bonding method using an organic insulating layer as an insulating layer. In the hybrid bonding method using an organic insulating layer, there may be a difference in thermal expansion between a terminal electrode made of metal or the like and the organic insulating layer due to heating at the time of bonding, and it is necessary to provide a predetermined level difference D between a tip end surface of the terminal electrode and a surface of the organic insulating layer in advance. In the present invention, in order to provide the level difference D, the surface of the semiconductor substrate 100 is irradiated with plasma (e.g. argon plasma). In this plasma irradiation, an organic insulating layer 102 is etched with plasma such that a surface 102a of the organic insulating layer 102 of the semiconductor substrate 100 is on the farther side than a tip end surface 103a of an electrode 103.

A composition for forming a protective film using a polymer having an imide group: cured under a film-forming condition in air and an inert gas; forming a protective film having excellent heat resistance, embedding and planarization ability for a pattern formed on a substrate, and good adhesiveness to the substrate; and forming a protective film having excellent resistance against an alkaline aqueous hydrogen peroxide. A composition for forming a protective film against alkaline aqueous hydrogen peroxide, including: (A) a polymer having a repeating unit represented by general formula (1A) having at least one or more fluorine atoms and at least one or more hydroxy groups, a terminal group is any one of the following general formulae (1B) and (1C); and organic solvent, wherein R.sub.1 represents any one group represented by the following formula (1D), and two or more kinds of R.sub.1 are optionally used in combination. ##STR00001##

The current disclosure relates to a method of etching etchable material from a semiconductor substrate. The method comprises providing a substrate comprising the etchable material into a reaction chamber and providing a haloalkylamine into the reaction chamber in vapor phase for etching the etchable material. The disclosure further relates to a semiconductor processing assembly, and to a method of cleaning a reaction chamber.

A semiconductor device includes a substrate and a bit line structure disposed on the substrate. The bit line structure includes a first conductive structure and a second conductive structure, in which a material of the first conductive structure includes polysilicon. The second conductive structure is disposed in direct contact on the first conductive structure, in which a reactivity of a material of the second conductive structure to oxygen is larger than a reactivity of tungsten to oxygen.

A method includes patterning a metal layer on a substrate to form two metal lines spaced apart from each other by a recess, forming a directed self-assembly (DSA) segment in the recess, wherein the DSA segment includes block co-polymer (BCP), performing a phase separation process on the DSA segment to cause two components of the BCP to separate from each other to form a first polymer block and a second polymer block that are aligned next to each other in the recess, and removing the second polymer block to form an air gap that is bordered by the first polymer block and that is located between the metal lines.

Several designs of a gas distribution device for a substrate processing system are provided. The gas distribution device includes a dual plenum showerhead. Additionally, designs for a light blocking structure used with the showerheads are also provided.

A process for forming a device can include forming a first semiconductor region having a first conductivity type. The process can include depositing a dielectric layer over the first semiconductor region, the dielectric layer having a first etch rate. The process can include forming a first photoresist layer having a second etch rate that is greater than the first etch rate over the dielectric layer and forming a second photoresist layer over the first photoresist layer. The process can include patterning the second photoresist layer to remove a region of the second photoresist, the first photoresist layer being exposed under the region. The process can include etching to form a beveled structure in the dielectric layer. The process can include removing the first photoresist layer and the second photoresist layer and performing ion implantation of the first semiconductor region with dopant species having a second conductivity type.

Selective gas etching for self-aligned pattern transfer uses a first block and a separate second block formed in a sacrificial layer to transfer critical dimensions to a desired final layer using a selective gas etching process. The first block is a first hardmask material that can be plasma etched using a first gas, and the second block is a second hardmask material that can be plasma etched using a second gas separate from the first gas. The first hardmask material is not plasma etched using the second gas, and the second hardmask material is not plasma etched using the first gas.

Embodiments described herein relate to plasma processes. A plasma process includes generating a plasma containing negatively charged oxygen ions. A substrate is exposed to the plasma. The substrate is disposed on a pedestal while being exposed to the plasma. While exposing the substrate to the plasma, a negative direct current (DC) bias voltage is applied to the pedestal to repel the negatively charged oxygen ions from the substrate.

Methods of forming microelectronic devices comprise forming a dielectric layer on a substrate, the dielectric layer comprising at least one feature defining a gap including sidewalls and a bottom. The methods include forming a hardmask on the dielectric layer; selectively depositing a self-assembled monolayer (SAM) on the bottom of the gap and on the hardmask; treating the microelectronic device with a plasma to remove the self-assembled monolayer (SAM) from the hardmask; forming a barrier layer on the dielectric layer and on the hardmask; selectively depositing a metal liner on the barrier layer on the sidewall; and performing a gap fill process on the metal liner.