A semiconductor device includes a conductive structure, a first dielectric layer, a second dielectric layer and a liner layer. The conductive structure is located on a substrate. The first dielectric layer covers the conductive structure and the substrate. The second dielectric layer is located on the first dielectric layer. An air gap is present in the first dielectric layer and the second dielectric layer, and is located above the conductive structure. The liner layer covers and surrounds a middle portion of the air gap.

A semiconductor device includes: a first conductive structure that comprises a first portion having sidewalls and a bottom surface, wherein the first conductive structure is embedded in a first dielectric layer; and an isolation layer comprising a first portion and a second portion, wherein the first portion of the isolation layer lines the sidewalls of the first portion of the first conductive structure, and the second portion of the isolation layer lines at least a portion of the bottom surface of the first portion of the first conductive structure.

A structure includes a first air gap including a first opening defined in a first dielectric layer and a second dielectric layer over the first opening and closing an end portion of the first opening. A second air gap may be over at least a portion of the first air gap. The second air gap includes a second opening defined in the second dielectric layer and a third dielectric layer over the second opening and closing an end portion of the second opening. The second air gap has a pointed lower end portion. In another version, the structure includes a first air gap in a first dielectric layer, a second dielectric layer over the first air gap, and a discrete dielectric member positioned in the second dielectric layer and aligned over the first air gap.

A semiconductor structure including a substrate, a conductive layer, and a semiconductor device is provided. The substrate includes a first surface, a second surface opposite to the first surface, at least one insulating vacancy extending from the first surface toward the second surface, and a through hole passing through the substrate. The conductive layer fills in the through hole. The semiconductor device is disposed on the second surface and is electrically connected to the conductive layer, and the at least one insulating vacancy is distributed corresponding to the semiconductor device.

A device includes an active region, a gate structure, a source/drain epitaxial structure, an epitaxial layer, a metal alloy layer, a contact, and a contact etch stop layer. The gate structure is across the active region. The source/drain epitaxial structure is over the active region and adjacent the gate structure. The epitaxial layer is over the source/drain epitaxial structure. The metal alloy layer is over the epitaxial layer. The contact is over the metal alloy layer. The contact etch stop layer lines sidewalls of the source/drain epitaxial structure. The metal alloy layer is spaced apart from the contact etch stop layer.

Semiconductor devices having air gap spacers that are formed as part of BEOL or MOL layers of the semiconductor devices are provided, as well as methods for fabricating such air gap spacers. For example, a method comprises forming a first metallic structure and a second metallic structure on a substrate, wherein the first and second metallic structures are disposed adjacent to each other with insulating material disposed between the first and second metallic structures. The insulating material is etched to form a space between the first and second metallic structures. A layer of dielectric material is deposited over the first and second metallic structures using a pinch-off deposition process to form an air gap in the space between the first and second metallic structures, wherein a portion of the air gap extends above an upper surface of at least one of the first metallic structure and the second metallic structure.

Provided are a gate contact structure and a method of manufacturing the gate contact structure. The gate contact structure includes a gate electrode, an etch stop layer on the gate electrode, a capping layer on the etch stop layer, the etch stop layer and the capping layer defining a contact hole penetrating therethrough, the contact hole including a first portion and a second portion, the first portion being in the etch stop layer and exposing the gate electrode, and the second portion being in the capping layer and in communication with the first portion, a liner along a side of the contact hole, and a gate contact plug being within the liner, wherein the etch stop layer, the gate electrode, and the liner define an air gap adjacent to the first portion of the contact hole.

A method for fabricating a semiconductor device includes the steps of first forming an inter-metal dielectric (IMD) layer on the logic region and the capacitor region of a substrate, forming a first metal interconnection in the IMD layer of the logic region and a second metal interconnection in the IMD layer of the capacitor region, removing the IMD layer adjacent to the second metal interconnection, and then forming a high-k dielectric layer on the first metal interconnection and extending to the second metal interconnection. Preferably, the high-k dielectric layer encloses an air gap.

A method includes depositing a dielectric layer over a substrate, and etching the dielectric layer to form an opening and to expose a first conductive feature underlying the dielectric layer. The dielectric layer is formed using a precursor including nitrogen therein. The method further includes depositing a sacrificial spacer layer extending into the opening, and patterning the sacrificial spacer layer to remove a bottom portion of the sacrificial spacer layer. A vertical portion of the sacrificial spacer layer in the opening and on sidewalls of the dielectric layer is left to form a ring. A second conductive feature is formed in the opening. The second conductive feature is encircled by the ring, and is over and electrically coupled to the first conductive feature. At least a portion of the ring is removed to form an air spacer.

A method for manufacturing an interconnect structure, includes: forming a first stack on a base structure, the first stack including a first conductive line and a first cap portion which is formed on the first conductive line; forming a second stack on the base structure, the second stack being spaced apart from the first stack by a dielectric portion, the second stack including a second conductive line, a second cap portion which is formed on the second conductive line, and a lower conductive via which is formed in the second cap portion; forming a patterned etch stop layer on the first stack, the second stack and the dielectric portion so that the lower conductive via is exposed from the patterned etch stop layer and the second conductive line is prevented from being exposed from the patterned etch stop layer; and forming an upper conductive via on the lower conductive via.