A semiconductor device with a small variation in characteristics is provided. The semiconductor device includes an oxide, a first conductor and a second conductor over the oxide, a first insulator over the first conductor, a second insulator over the second conductor, a third conductor over the first insulator, a fourth insulator over the second insulator, a fifth insulator over the third insulator and the fourth insulator, a sixth insulator over the fifth insulator, a seventh insulator that is over the oxide and placed between the first conductor and the second conductor, an eighth insulator over the seventh insulator, a third conductor over the eighth insulator, and a ninth insulator over the third conductor and the sixth to eighth insulators. The third conductor includes a region overlapping the oxide. The seventh insulator includes a region in contact with each of the oxide, the first conductor, the second conductor, and the first to sixth insulators. The first insulator, the second insulator, the fifth insulator, and the ninth insulator are each a metal oxide having an amorphous structure.

The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate, a plurality of through-substrate vias (TSVs), a plurality of insulating segments, and a plurality of liners. The substrate includes a first surface and a second surface opposite to the first surface. The plurality of TSVs penetrate through the substrate. Each of the insulating segments includes an embedded portion disposed in the TSV, and an extension portion disposed over the embedded portion and the first surface. The liner is disposed on a side surface of the TSV and between the side surface and the embedded portion of the insulating segment. The plurality of insulating segments and the plurality of liners are exposed by the second surface of the substrate.

Semiconductor devices and methods are disclosed, including memory cells/memory strings, semiconductor devices and systems. Example semiconductor devices and methods include a stack of alternating dielectric layers and conductor layers, and a vertical conductor passing between a top level of the stack and a bottom level of the stack. Lateral connections are included between a location along the vertical conductor and a selected conductor layer from the stack, wherein a direct interface is formed between the vertical conductor and the selected conductor layer.

The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate, a plurality of through-substrate vias (TSVs), a plurality of insulating segments, and a plurality of liners. The substrate includes a first surface and a second surface opposite to the first surface. The plurality of TSVs penetrate through the substrate. Each of the insulating segments includes an embedded portion disposed in the TSV, and an extension portion disposed over the embedded portion and the first surface. The liner is disposed on a side surface of the TSV and between the side surface and the embedded portion of the insulating segment. The plurality of insulating segments and the plurality of liners are exposed by the second surface of the substrate.

Provided are an interconnection structure and a method of forming the same. The interconnection structure includes a substrate, including a lower voltage device region and a higher voltage device region; a first dielectric layer, located on the substrate in the lower voltage device region and the higher voltage device region; an under-layer interconnection structure, located in the first dielectric layer in the lower voltage device region and the higher voltage device region; a second dielectric layer, located on the first dielectric layer in the lower voltage device region and the higher voltage device region; a first via plug and a first metal layer, located in the second dielectric layer in the lower voltage device region; and a U-shaped high k (dielectric constant) layer and a second metal layer, located in the second dielectric layer in the higher voltage device region.

A semiconductor structure includes a semiconductor substrate, a dielectric layer, a via, a first graphene layer, and a metal line. The dielectric layer is over the semiconductor substrate. The via extends through the dielectric layer. The first graphene layer extends along a top surface of the via. The metal line spans the first graphene layer. The metal line has a line width decreasing as a distance from the first graphene layer increases.

A semiconductor structure includes a fin structure formed over a substrate. The structure also includes a gate structure formed across the fin structure. The structure also includes source/drain epitaxial structures formed on opposite sides of the gate structure. The structure also includes an inter-layer dielectric (ILD) structure formed over the gate structure. The structure also includes a contact blocking structure formed through the ILD structure over the source/drain epitaxial structure. A lower portion of the contact blocking structure is surrounded by an air gap, and the air gap is covered by a portion of the ILD structure.

An integrated circuit includes (i) a first transistor device having a first source or drain region coupled to a first source or drain contact, and a first gate electrode, (ii) a second transistor device having a second source or drain region coupled to a second source or drain contact, and a second gate electrode, (iii) a first dielectric material above the first and second source or drain contacts, (iv) a second dielectric material above the first and second gate electrodes, (v) a third dielectric material above the first and second dielectric materials, and (vi) an interconnect feature above and conductively coupled to the first source or drain contact. In an example, the interconnect feature comprises an upper body of conductive material extending within the third dielectric material, and a lower body of conductive material extending within the first dielectric material, with an interface between the upper and lower bodies.

A circuit structure and a method of manufacturing a circuit structure are provided. The circuit structure includes a first metal line and a second metal line. The second metal line is disposed over the first metal line. At least one air gap is disposed between the first metal line and the second metal line.

A semiconductor device structure, along with methods of forming such, are described. The structure includes a plurality of source/drain regions, an interconnect structure disposed over the plurality of source/drain regions, a backside interconnect structure disposed below the plurality of source/drain regions, and a first conductive feature disposed in the backside interconnect structure. The first conductive feature is electrically connected to a first number of source/drain regions of the plurality of source/drain regions. The structure further includes a second number of memory devices disposed in the backside interconnect structure, the memory devices are electrically connected to the first conductive feature, and the second number is different from the first number.