A semiconductor structure manufacturing method includes forming a base having a substrate and a dielectric layer on the substrate; forming a first metal layer on the base, the first metal layer has a plurality of first metal lines spaced apart from each other and partially covers the base; forming a dielectric landing layer to cover top surfaces and sidewalls of the plurality of first metal lines; forming a hollow dielectric layer on the dielectric landing layer between adjacent first metal lines; forming an interlayer dielectric layer to cover top surfaces of the hollow dielectric layer and the dielectric landing layer; etching the interlayer dielectric layer and the dielectric landing layer to form a plurality of trenches that expose the plurality of first metal lines; and depositing a metal material in the plurality of trenches to form a second metal layer.

A semiconductor structure includes: an electrode cover layer; a first conductive structure on the electrode cover layer; a contact structure, including a first and a first contact layer. The first contact layer is in contact with the first conductive structure, the bottom of the second contact layer is in contact with the top of the first contact layer, the width of the first contact layer is greater than the width of the bottom of the second contact layer, the lower surface of the contact structure is not lower than the lower surface of the electrode cover layer, and the resistivity of the first conductive structure is not greater than that of the contact structure and is not greater than that of the electrode cover layer.

Methods, systems, and devices for staircase formation in a memory array are described. A liner composed of a first liner material may be deposited on a tread and a first portion of the liner may be doped. After doping the first portion of the liner, a second portion of the liner may be converted into a second liner material using a chemical process. After converting the second portion of the liner into the second liner material, the first portion of the liner material may be removed so that a subsequent removal process can expose a first sub-tread. After exposing the first sub-tread, the second portion of the liner may be removed so that a second sub-tread is exposed.

A conductive hard mask layer can be patterned with peripheral discrete openings. An anisotropic etch process can be performed to form peripheral discrete via cavities, which are subsequently expanded to form a continuous moat trench. An edge seal structure can be formed in the continuous moat trench. Alternatively, a conductive bridge structure may be formed prior to formation of a patterned conductive hard mask layer, and a moat trench can be formed around a periphery of the semiconductor die while the conductive bridge structure provides electrical connection between an inner portion and an outer portion of the conductive hard mask layer. The entire conductive hard mask layer can be electrically connected to a semiconductor substrate to reduce or prevent arcing during an anisotropic etch process that forms the peripheral discrete via cavities or the moat trench.

Approaches of the disclosure relate to methods for forming self-aligned backside contacts in a semiconductor device. One method may include forming a trench in a stack of layers, wherein the stack of layers comprises a plurality of alternating first layers and second layers atop a base layer, and wherein the trench is defined by a set of sidewalls and a bottom extending between the set of sidewalls. The method may further include implanting the bottom of the trench to form an etch stop layer within the base layer, forming a recess in the base layer by removing the base layer selective to the etch stop layer, and filling the recess with a temporary material. The method may further include depositing a source/drain material within the trench, wherein the source/drain material is formed over the temporary material.

A semiconductor device includes a substrate having a first and second surface opposite to each other, and an active region on the first surface and defined by a first isolation region; a plurality of active fins on the active region, extending in a first direction, and defined by a second isolation region having a second depth smaller than a first depth of the first isolation region; a buried conductive wiring in a trench adjacent to the fins, and extending in a direction of the trench; a filling insulation portion in the trench, and having the wiring therein; an interlayer insulation layer on the first and second isolation regions and on the buried conductive wiring; a contact structure penetrating the interlayer insulation layer, and contacting the buried conductive wiring; and a conductive through structure extending through the substrate from the second surface to the trench, and contacting the buried conductive wiring.

An MIM capacitor structure includes a dielectric layer. An MIM capacitor body is disposed on the dielectric layer. The MIM capacitor body includes a first electrode and a second electrode stacked alternately and a capacitor dielectric layer disposed between the first electrode and the second electrode. The first electrode has a first extension part extending out from the MIM capacitor body. The second electrode has a second extension part extending out from the MIM capacitor body. The first extension part includes a first aluminum-containing material layer. The second extension part includes a second aluminum-containing material layer. A first conductive plug penetrates the first extension part, wherein the first conductive plug has a first arc which is concave toward the first aluminum-containing material layer. A second conductive plug penetrates the second extension part, wherein the second conductive plug has a second arc which is concave toward the second aluminum-containing material layer.

A method of manufacturing a semiconductor device comprising: forming a first layer in which first conductive patterns and first dielectric patterns are alternately arranged; forming passivation layers on the first conductive patterns, respectively; and forming second dielectric patterns on the first dielectric patterns, respectively, by an area-selective atomic layer deposition at a first temperature, wherein the first temperature is 350 C. or less, wherein the area-selective atomic layer deposition includes: pulsing a metal catalyst; performing a primary purge by a purge gas; sub-pulsing a reaction precursor at least once; and performing a secondary purge by the purge gas after each of the sub-pulsing.

A semiconductor memory device, and a method of manufacturing the semiconductor memory device, includes: a substrate including a peripheral circuit, a gate stack structure disposed over the substrate and including a cell array region and a stepped region that extends from the cell array region, a channel structure passing through the cell array region of the gate stack structure, a memory layer surrounding a sidewall of the channel structure, a first contact plug passing through the stepped region of the gate stack structure, and an insulating structure surrounding a sidewall of the first contact plug to insulate the first contact plug from the gate stack structure.

A semiconductor device includes a lower insulating film that includes a first and second trenches on a substrate, a first wiring in the first trench, a second wiring in the second trench, a capping insulating film including an insulating recess portion and an insulating liner portion, an upper insulating film on the capping insulating film, and an upper contact that penetrates the capping insulating film and connects to the first wiring, The insulating recess portion is in the second trench and the insulating liner portion extends along an upper surface of the lower insulating film. The upper contact includes a contact recess portion in the first trench, an extended portion connected to the contact recess portion, and a plug portion connected to the extended portion inside the upper insulating film. A width of the extended portion is greater than a width of the plug portion.