Memory circuitry comprising strings of memory cells comprises laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers. Channel-material strings of memory cells extend through the insulative tiers and the conductive tiers in a memory-array region. The insulative tiers and the conductive tiers of the laterally-spaced memory blocks extend from the memory-array region into a stair-step region. Individual stairs in the stair-step region comprise one of the conductive tiers. Conductive vias are individually directly against conducting material that is in the one conductive tier in one of the individual stairs. Insulator material in the stair-step region is directly above the stairs. An insulative-material lining is circumferentially around and extends elevationally along individual of the conductive vias between the individual conductive vias and the insulator material. Individual of the insulative-material linings and the insulator material comprise an interface there-between. Other embodiments, including methods, are disclosed.

Methods for forming a back-end-of-line (BEOL) passive device structure are provided. A method according to the present disclosure includes depositing a first conductor layer over a substrate, patterning the first conductor layer to form a patterned first conductor layer, depositing a first insulation layer over the patterned first conductor layer, depositing a second conductor layer over the first insulation layer, patterning the second conductor layer to form a patterned second conductor layer, depositing a second insulation layer over the patterned second conductor layer, depositing a third conductor layer over the second insulation layer, and patterning the third conductor layer to form a patterned third conductor layer. The patterning of the first conductor layer includes removing a right-angle edge of the first conductor layer.

The present disclosure provides a semiconductor structure. The semiconductor structure includes: a substrate; a transistor on the substrate; a first dielectric layer over the transistor; a second dielectric layer over the first dielectric layer; a barrier layer extending from the second dielectric layer to the first dielectric layer; and a conductive structure separated from the second dielectric layer and the first dielectric layer by the barrier layer. The barrier layer includes: a first layer, including titanium or tantalum along inner sidewalls of the first dielectric layer and the second dielectric layer; a second layer, being an oxide of titanium or tantalum and over the first layer; and a third layer, including cobalt and over the second layer.

A method is described. The method includes creating a partial through-substrate via (TSV) plug in a front side of a wafer, the partial TSV having a front side and a back side. The back side of the partial TSV extending toward a front side of a substrate but not into a bulk of the substrate. A cavity is etched in a back side of the wafer that exposes the partial TSV plug. An insulator is applied to the etched back side of the wafer. A portion of the partial TSV plug is exposed by removing a portion of the insulator. A conductive material is deposited to connect the exposed, partial TSV plug to a surface on the back side of the wafer.

Devices and methods that include for configuring a profile of a liner layer before filling an opening disposed over a semiconductor substrate. The liner layer has a first thickness at the bottom of the opening and a second thickness a top of the opening, the second thickness being smaller that the first thickness. In an embodiment, the filled opening provides a contact structure.

A device includes a dielectric layer and a conductor in the dielectric layer including a first conductive material. A conductive liner wraps around the conductor and includes a second conductive material. A barrier layer is at an interface between the conductive liner and the dielectric layer, including a first oxide and a second oxide.

Examples of an integrated circuit with an interconnect structure and a method for forming the integrated circuit are provided herein. In some examples, the method includes receiving a workpiece that includes a substrate and an interconnect structure. The interconnect structure includes a first conductive feature disposed within a first inter-level dielectric layer. A blocking layer is selectively formed on the first conductive feature without forming the blocking layer on the first inter-level dielectric layer. An alignment feature is selectively formed on the first inter-level dielectric layer without forming the alignment feature on the blocking layer. The blocking layer is removed from the first conductive feature, and a second inter-level dielectric layer is formed on the alignment feature and on the first conductive feature. The second inter-level dielectric layer is patterned to define a recess for a second conductive feature, and the second conductive feature is formed within the recess.

Microelectronic deviceshaving at least one conductive contact structure adjacent a silicide regionare formed using methods that avoid unintentional contact expansion and contact reduction. A first metal nitride liner is formed in a contact opening, and an exposed surface of a polysilicon structure is thereafter treated (e.g., cleaned and dried) in preparation for formation of a silicide region. During the pretreatments (e.g., cleaning and drying), neighboring dielectric material is protected by the presence of the metal nitride liner, inhibiting expansion of the contact opening. After forming the silicide region, a second metal nitride liner is formed on the silicide region before a conductive material is formed to fill the contact opening and form a conductive contact structure (e.g., a memory cell contact structure, a peripheral contact structure).

A method for forming a semiconductor device structure is provided. The method includes forming a first conductive structure surrounded by a first dielectric layer and forming a second dielectric layer over the first conductive structure and the first dielectric layer. The method also includes forming a via hole in the second dielectric layer, and the via hole exposes the first conductive structure. The method further includes partially removing the first conductive structure through the via hole to form a recess in the first conductive structure. In addition, the method includes forming a second conductive structure filling the recess and the via hole.

Increasing in a contact-resistance between a trench gate lead-out electrode and a gate lead-out contact member is suppressed. It is assumed that a natural oxidation film is formed in the polysilicon film when the trench gate lead-out electrode is formed. In case of the natural oxidation film is formed, a desired etching process is performed so that the natural oxidation film does not protrude beyond the upper surface of the trench gate lead-out electrode.