A semiconductor package includes a semiconductor die, a device layer over the semiconductor die and including an optical device, an insulator layer over the device layer, a buffer layer over the insulator layer, an etch stop layer between the device layer and the insulator layer, a connective terminal, and a bonding via passing through the device layer and electrically connecting the semiconductor die to the connective terminal. The conductive terminal passes through the etch stop layer, the insulator layer, and the buffer layer. The conductive terminal is in direct contact with the etch stop layer.

An electronic device includes a multilevel package substrate with a horizontal substrate integrated waveguide (SIW) with a channel, a vertical SIW with an opening, a grounded coplanar waveguide (GCPW), a first transition between the horizontal SIW and the GCPW, and a second transition between the horizontal and vertical SIWs, as well as a semiconductor die having conductive structures coupled to a signal trace and a ground trace of the GCPW, and a package structure that encloses the semiconductor die and a portion of the multilevel package substrate.

The present invention provides a packaging structure and a manufacturing method thereof. The packaging structure includes a first substrate, a first chip, a second chip, a first heat conductor and a second heat conductor, wherein the first substrate includes a cavity; the first chip is embedded in the cavity and includes a first connecting surface and a first heat-conducting surface that face away from each other; the second chip is disposed on a side of the first connecting surface and electrically connected to the first chip, a side of the second chip distal from the first chip includes a second heat-conducting surface on a side; and the first heat conductor is connected to the first heat-conducting surface, and the second heat conductor is connected to the second heat-conducting surface. The first substrate includes a third connecting surface that is flush with the first connecting surface.

A multiple die package is described that has an embedded bridge to connect the dies. One example is a microelectronic package that includes a package substrate, a silicon bridge embedded in the substrate, a first interconnect having a first plurality of contacts at a first location of the silicon bridge, a second interconnect having a second plurality of contacts at a second location of the silicon bridge, a third interconnect having a third plurality of contacts at a third location of the silicon bridge, and an electrically conductive line in the silicon bridge connecting a contact of the first interconnect, a contact of the second interconnect, and a contact of the third interconnect each to each other.

Provided is a flux that can suppress the generation of voids when an indium alloy sheet is used to perform a continuous reflow under different temperature conditions. The present invention employs a flux that contains a rosin ester, an organic acid (A), and a solvent (S). The organic acid (A) includes a dimer acid (A1) that demonstrates a weight reduction rate of not more than 1 mass % in a thermogravimetric analysis in which the dimer acid is heated up to 260 C. at a temperature rising rate of 10 C./min. The solvent (S) includes a solvent (S1) that demonstrates the weight reduction rate of at least 99 mass % in a thermogravimetric analysis in which the solvent (S1) is heated up to 150 C. at a temperature rising rate of 6 C./min.

A package comprising a metallization portion; an integrated device comprising a plurality of pillar interconnects, wherein the integrated device is coupled to the metallization portion through the plurality of pillar interconnects; and an encapsulation layer at least partially encapsulating the integrated device, wherein the encapsulation layer is coupled to the metallization portion.

A semiconductor package structure includes a redistribution structure layer, at least one chip, an encapsulant, and multiple solder balls. The redistribution structure layer includes multiple first connectors located on a first side. Each first connector includes a connecting pad, a soldering pad, and multiple conductive blind holes located between the connecting pad and the soldering pad. The conductive blind holes are disposed separately from each other and connect the connecting pad and the soldering pad. The chip is disposed on a second side of the redistribution structure layer and electrically connected to the redistribution structure layer. The encapsulant is disposed on the second side and at least covers the chip and the second side. The solder balls are disposed on the first side of the redistribution structure layer and electrically connected to the redistribution structure layer. The solder balls are respectively connected to the connecting pad of each first connector.

Implementations of a semiconductor package may include two or more die, each of the two more die coupled to a metal layer at a drain of each of the two more die, the two or more die and each metal layer arranged in two parallel planes; a first interconnect layer coupled at a source of each of the two more die; a second interconnect layer coupled to a gate of each of the two or more die and to a gate package contact through one or more vias; and an encapsulant that encapsulates the two or more die and at least a portion of the first interconnect layer, each metal layer, and the second interconnect layer.

A semiconductor device includes a semiconductor element, a sealing member, and a rewiring layer. The rewiring layer includes an insulating layer covering a front surface of the semiconductor element and a part of the sealing member, an electrode connected to the semiconductor element, and an externally-exposed layer being conductive and covering a portion of the electrode exposed from the insulating layer.

A semiconductor device assembly can include a first semiconductor device comprising CMOS circuitry at a first active surface and a second semiconductor device having a footprint smaller than that of the first semiconductor device and including memory array circuitry at a second active surface hybrid-bonded to the first active surface. The assembly can further include a gapfill material directly contacting the first active surface of the first semiconductor device and having an upper surface coplanar with a back surface of the second semiconductor device, and a metallization layer disposed over the second semiconductor device and the gapfill material. The metallization layer can include conductive structures operably coupled to the second semiconductor device through back-side contacts of the second semiconductor device. The assembly can further include a plurality of bond pads disposed at an upper surface of the metallization layer and coupled to the conductive structures of the metallization layer.