A method of forming a semiconductor device is provided. The method includes forming an interposer including a plurality of conductive vias, each conductive via having a first end exposed at a first major side of an interposer substrate and a second end exposed at a second major side of the interposer substrate. A semiconductor die is mounted on the first major side of the interposer substrate. An encapsulant encapsulates the semiconductor die and portions of the first major side of the interposer substrate. A redistribution layer structure is formed over the second major side of the interposer substrate such that the semiconductor die interconnected with the redistribution layer structure by way of the interposer.

A substrate is disclosed. In one embodiment, the substrate comprises a substrate core including a plurality of through holes located therethrough, a plurality of metal pins aligned in the plurality of through holes, and at least one layer deposited on at least one of top and bottom surfaces of the substrate core. In one embodiment, the plurality of metal pins are aligned with the plurality of through holes such that each of the plurality of metal pins extends at least to both the top and bottom surface of the substate core. In some embodiments, the deposited at least one layer is deposited after the plurality of metal pins have been aligned in the through holes of the substrate core.

In one example, an electronic device includes a first substrate, an electronic component disposed over a side of the first substrate, and a vertical interconnect structure coupled to the side of the first substrate. The vertical interconnect structure comprises a first metallic core structure coupled to the side of the first substrate, a second metallic core structure coupled to the first metallic core structure, and a fusible material coupling the first metallic core structure with the second metallic core structure. The fusible material also couples the first metallic core structure to the first substrate. A second substrate can be disposed over the electronic component and the vertical interconnect structure. The second metallic core structure of the vertical interconnect structure can be coupled to the second substrate by the fusible material. An encapsulant can be disposed over the electronic component. Other examples and related methods are also disclosed herein.

A semiconductor device assembly is provided. The assembly includes a package substrate which has a tunneled interconnect structure. The tunneled interconnect structure has a solder-wettable surface, an interior cavity, and at least one microvia extending from the surface to the cavity. The assembly further includes a semiconductor device disposed over the substrate and a solder joint coupling the device and the substrate. The joint comprises the solder between the semiconductor device and the interconnect structure, which includes the solder on the surface, the solder in the microvia, and the solder within the interior cavity.

A display device includes a substrate, a plurality of light-emitting elements and a plurality of transistors provided to the substrate, a first organic insulating film that is provided covering the transistors and is in direct contact with at least one of a source electrode and a drain electrode of the transistors, an anode electrode provided on the first organic insulating film and electrically coupled to each of the light-emitting elements, a cavity formed in the first organic insulating film and recessed toward the substrate, and a reflective layer provided covering a side and a bottom of the cavity formed in the first organic insulating film.

Embodiments provide a method and resulting structure that includes forming an opening in a dielectric layer to expose a metal feature, selectively depositing a metal cap on the metal feature, depositing a barrier layer over the metal cap, and depositing a conductive fill on the barrier layer.

A semiconductor device is provided. The semiconductor device comprises a semiconductor die comprising a semiconductor substrate and a plurality of transistors arranged at a front side of the semiconductor substrate. Further, the semiconductor die comprises a first electrically conductive structure extending from the front side of the semiconductor substrate to a backside of the semiconductor substrate and a second electrically conductive structure extending from the front side of the semiconductor substrate to the backside of the semiconductor substrate. The semiconductor device further comprises an interposer directly attached to the backside of the semiconductor substrate. The interposer comprises a first trace electrically connected to the first electrically conductive structure of the semiconductor die. Further the interposer comprises the first trace or a second trace electrically connected to the second electrically conductive structure of the semiconductor die.

A semiconductor structure includes a first dielectric layer over a metal line and a redistribution layer (RDL) over the first dielectric layer. The RDL is electrically connected to the metal line. The RDL has a curved top surface and a footing feature, where the footing feature extends laterally from a side surface of the RDL. A second dielectric layer is disposed over the RDL, where the second dielectric layer also has a curved top surface.

A semiconductor device includes a first substrate and a second substrate. A graphene-coated interconnect is disposed between the first substrate and second substrate. A semiconductor die is disposed between the first substrate and second substrate. The first substrate is electrically coupled to the second substrate through the graphene-coated interconnect. An encapsulant is deposited between the first substrate and second substrate.

A semiconductor package includes a first redistribution structure, a first die above the first redistribution structure, a second die above the first die, a heat dissipation unit on side surfaces of the first die or the second die, and a second redistribution structure above the second die. The semiconductor package includes a first post protruding from an upper surface of the first redistribution structure and extending to a lower surface of the second redistribution structure, a second post connecting the heat dissipation unit with a heat dissipation redistribution structure as a thermal path, and a molding unit filling an empty space between the first redistribution structure and the second redistribution structure. An outer pad of the heat dissipation redistribution structure is exposed to an outside of the semiconductor package, and an inner pad of the heat dissipation redistribution structure is in contact with the second post.