A package structure is provided. The package structure includes a substrate and a semiconductor chip over the substrate. The package structure also includes a protective film laterally surrounding the semiconductor chip. The package structure further includes an underfill element between the semiconductor chip and the protective film. A portion of the underfill element is directly below the protective film.

Provided is a package structure, including a substrate, a chip on the substrate in a flip-chip manner, the chip including a circuit layer, and a side heat dissipator on a side of the chip, the side heat dissipator comprising a heat conduction material, wherein the side heat dissipator is electrically connected to the circuit layer.

A semiconductor chip having at least two electrical contact points which are arranged on a main surface of the semiconductor chip is disclosed, a metallic reservoir layer being applied over the entire surface over or on the electrical contact point. A diffusion barrier layer is applied in direct contact on the metallic reservoir layer, the diffusion barrier layer being arranged offset with respect to the metallic reservoir layer, so that the metallic reservoir layer is partially freely accessible. In this case, the diffusion barrier layer forms an adhesion surface for a solder and/or a first solder component of the solder and/or a second solder component of the solder. Methods for connecting a semiconductor chip to a connection carrier are also given.

The package-on-package (POP) structure includes a first package unit of three-dimensional fan-out memory chips and a SiP package unit of the two-dimensional fan-out peripheral circuit chip. The first package unit includes: memory chips laminated in a stepped configuration; a molded substrate; wire bonding structures; a first rewiring layer; a first encapsulating layer; and first metal bumps, formed on the first rewiring layer. The SiP package unit includes: a second rewiring layer; a peripheral circuit chip; a third rewiring layer, bonded to the circuit chip; first metal connection pillars; a second encapsulating layer for the circuit chip and the first metal connection pillars; and second metal bumps on the second rewiring layer. The first metal bumps are bonded to the third rewiring layer. Integrating the two package units into the POP is enabled by three rewiring layers and the molded substrate which supports the first package unit during wire bonding process.

A semiconductor device of an embodiment includes: a first semiconductor element; a first insulating resin that seals the first semiconductor element; a wiring substrate having a pad; a first wiring that extends from the first semiconductor element toward the wiring substrate, and has a first head portion and a first column portion, the first column portion connected to the first semiconductor element and the first head portion exposed on a surface of the first insulating resin; and a first conductive bonding agent that electrically connects the first head portion of the first wiring and the pad. When a surface of the first head portion facing a side of the first insulating resin is defined as a first surface. A surface of the first insulating resin on a side of the wiring substrate is defined as a second surface. A distance from a surface of the wiring substrate on a side of the first insulating resin to the first surface is defined as a first distance, and a distance from a surface of the wiring substrate on the side of the first insulating resin to the second surface is defined as a second distance. The first distance is shorter than the second distance.

Various aspects of the present disclosure generally relate to integrated circuit devices, and to a conductive structure with multiple support pillars. A device includes a die including a contact pad. The device also includes a conductive structure. The conductive structure includes multiple support pillars coupled to the die, a bridge coupled to each of the multiple support pillars, and a cap pillar coupled to the bridge opposite the multiple support pillars. The device further includes a solder cap coupled to the cap pillar. The solder cap is electrically connected to the contact pad via the cap pillar, the bridge, and at least one of the multiple support pillars.

An offset interposer includes a land side including land-side ball-grid array (BGA) and a package-on-package (POP) side including a POP-side BGA. The land-side BGA includes two adjacent, spaced-apart land-side pads, and the POP-side BGA includes two adjacent, spaced-apart POP-side pads that are coupled to the respective two land-side BGA pads through the offset interposer. The land-side BGA is configured to interface with a first-level interconnect. The POP-side BGA is configured to interface with a POP substrate. Each of the two land-side pads has a different footprint than the respective two POP-side pads.

Methods of making a semiconductor device assembly are provided. The methods can comprise providing a first semiconductor device having a first dielectric material at a first surface, providing a carrier wafer having a second dielectric material at a second surface, and forming a dielectric-dielectric bond between the first dielectric material and the second dielectric material. At least one of the first surface and the second surface includes a region of hydrophobic material electrically isolated from any circuitry of the first semiconductor device and configured to have a reduced bonding strength to a facing region relative to the dielectric-dielectric bond. The method can further include stacking one or more second semiconductor devices over the first semiconductor device to form the semiconductor device assembly, and removing the semiconductor device assembly from the carrier wafer.

Provided are a semiconductor structure and a method of forming the same. The semiconductor structure includes: a substrate, an under bump metallurgy (UBM) structure, and a solder. The UBM structure is disposed over the substrate. The UBM structure includes a first metal layer; a second metal layer disposed on the first metal layer; and a third metal layer disposed on the second metal layer. A sidewall of the first metal layer is substantially aligned with a sidewall of the second metal layer, and a sidewall of the third metal layer is laterally offset inwardly from the sidewalls of the first and second metal layers. The solder is disposed on the third metal layer.

An electronic device includes: a first insulating layer; a first metal bump disposed on the first insulating layer; a second insulating layer disposed on the first metal bump; a metal layer, wherein the first insulating layer is disposed between the second insulating layer and the metal layer; a second metal bump disposed between the metal layer and the first insulating layer, wherein the second metal bump electrically connects to the first metal bump; a third insulating layer disposed between the second metal bump and the first insulating layer, wherein the third insulating layer includes an opening exposing a portion of the second metal bump; and a fourth insulating layer disposed between the third insulating layer and the first insulating layer, wherein a portion of the fourth insulating layer extends and is disposed in the opening to contact the second metal bump.