A display panel including a circuit board having first pads, light emitting devices disposed on the circuit board and having second pads and including at least one first light emitting device to emit light having a first peak wavelength and second light emitting devices to emit light having a second peak wavelength, and a metal bonding layer electrically connecting the first pads and the second pads, in which the metal bonding layer of the first light emitting device has a thickness different from that of the metal bonding layer of the second light emitting devices while including a same material, and a surface of the second light devices are disposed at an elevation between an upper surface and a bottom surface of the first light emitting device.

A semiconductor package includes a redistribution layer including, a first insulating layer including a first trench, a first conductive layer including a first conductive region extending along a top surface of the first insulating layer and a second conductive region disposed inside the first trench, a second insulating layer on the first conductive layer and the first insulating layer, the second insulating layer including a second trench at least partially overlapping the first trench, the second trench exposing a part of the first conductive region and a second conductive layer including a third conductive region extending along a top surface of the second insulating layer and a fourth conductive region disposed on the second conductive region inside a via trench including sidewalls of the first trench and the second trench, and wherein the second and fourth conductive regions have a width in a range of 20 m to 600 m.

Integrated circuit assemblies can be fabricated on a wafer scale, wherein a base template, having a plurality of openings, may cover a base substrate, such as a die wafer, wherein the base substrate has a plurality of first integrated circuit devices formed therein and wherein at least one second integrated circuit device is electrically attached to a corresponding first integrated circuit device through a respective opening in the base template. Thus, when the base substrate and base template are singulated into individual integrated circuit assemblies, the individual integrated circuit assemblies will each have a first integrated circuit that is edge aligned to a singulated portion of the base template. The singulated portion of the base template can provide an improved thermal path, mechanical strength, and/or electrical paths for the individual integrated circuit assemblies.

A method of electroplating a metal into features, having substantially different depths, of a partially fabricated electronic device on a substrate is provided. The method includes adsorbing accelerator into the bottom of recessed features; partially filling the features by a bottom up fill mechanism in an electroplating solution; diffusing leveler into shallow features to decrease the plating rate in shallow features as compared to deep features; and electroplating more metal into the features such that the height of metal in deep features is similar to the height of metal in shallow features.

Methods for forming semiconductor structures are provided. The method for forming a semiconductor structure includes forming a metal pad over a first substrate and forming a polymer layer over the metal pad. The method for forming a semiconductor structure further includes forming a seed layer over the metal pad and extending over the polymer layer and forming a conductive pillar over the seed layer. The method for forming a semiconductor structure further includes wet etching the seed layer using an etchant comprising H2O2. In addition, the step of wet etching the seed layer is configured to form an extending portion having a slope sidewall.

A vertical solid state device comprising: a connection pad; and side walls comprising a metal-insulator-semiconductor (MIS) structure; wherein a gate of the MIS structure is shorted to at least one contact of the vertical solid state device and a threshold voltage (VT) of the MIS structure is adjusted to increase the efficiency of the device.

A semiconductor package including: a semiconductor package comprising a first semiconductor chip which includes a first face and a second face opposite to each other in a first direction, a first insulating layer which is disposed on the first face, and includes vias connected to each connecting pad of the first semiconductor chip, redistribution patterns which are disposed on the first insulating layer, under bump metal layers (UBM) which are respectively disposed on the redistribution patterns, a second insulating layer which covers a part of each of the redistribution patterns, and solder bumps which are respectively disposed on the UBMs, wherein the first insulating layer includes a third face and a fourth face opposite to the third face in the first direction, wherein the third face is adjacent to the first face, and a part of the fourth face does not overlap the second insulating layer in the first direction.

A semiconductor package is provided. The semiconductor package includes a semiconductor device bonded to a base through a first conductive structure. The semiconductor device includes a carrier substrate including a conductive trace. A portion of the conductive trace is elongated. The semiconductor device also includes a second conductive structure above the carrier substrate. A portion of the second conductive structure is in contact with the portion of the conductive trace. The semiconductor device further includes a semiconductor body mounted above the conductive trace. The semiconductor body is connected to the second conductive structure.

A method includes: providing a passivation layer with an embedded MIM capacitor; forming a redistribution layer (RDL) above the passivation layer; and forming an opening in the RDL above the MIM capacitor, wherein the opening separates the RDL into first and second RDL structures, wherein each of the first and second RDL structures has a convex-shaped profile on a sidewall that defines the opening that separates the first RDL structure from the second RDL structure, and wherein the convex-shaped profile on the sidewalls resists stress migration from the RDL to the MIM capacitor to resist stress migration induced cracks forming in the MIM capacitor. The forming an opening includes: removing a portion of the RDL to a first depth using first etching operations; and removing a portion of the RDL to a second depth by laterally etching sidewalls of the first and second RDL structures.

The present disclosure is directed to embodiments of a conductive structure on a conductive barrier layer that separates the conductive structure from a conductive layer on which the conductive barrier layer is present. A gap or crevice extends along respective surfaces of the conductive structure and along respective surfaces of one or more insulating layers. The gap or crevice separates the respective surfaces of the one or more insulating layers from the respective surfaces of the conductive structure. The gap or crevice provides clearance in which the conductive structure may expand into when exposed to changes in temperature. For example, when coupling a wire bond to the conductive structure, the conductive structure may increase in temperature and expand into the gap or crevice. However, even in the expanded state, respective surfaces of the conductive structure do not physically contact the respective surfaces of the one or more insulating layers.