Embodiments of the present disclosure generally relate to a method of processing a substrate. The method includes exposing the substrate positioned in a processing volume of a processing chamber to a hydrocarbon-containing gas mixture, exposing the substrate to a boron-containing gas mixture, and generating a radio frequency (RF) plasma in the processing volume to deposit a boron-carbon film on the substrate. The hydrocarbon-containing gas mixture and the boron-containing gas mixture are flowed into the processing volume at a precursor ratio of (boron-containing gas mixture/((boron-containing gas mixture)+hydrocarbon-containing gas mixture) of about 0.38 to about 0.85. The boron-carbon hardmask film provides high modulus, etch selectivity, and stress for high aspect-ratio features (e.g., 10:1 or above) and smaller dimension devices (e.g., 7 nm node or below).

An embodiment method includes: forming fins extending from a semiconductor substrate; depositing an inter-layer dielectric (ILD) layer on the fins; forming masking layers on the ILD layer; forming a cut mask on the masking layers, the cut mask including a first dielectric material, the cut mask having first openings exposing the masking layers, each of the first openings surrounded on all sides by the first dielectric material; forming a line mask on the cut mask and in the first openings, the line mask having slot openings, the slot openings exposing portions of the cut mask and portions of the masking layers, the slot openings being strips extending perpendicular to the fins; patterning the masking layers by etching the portions of the masking layers exposed by the first openings and the slot openings; and etching contact openings in the ILD layer using the patterned masking layers as an etching mask.

Exemplary semiconductor processing methods may include providing an oxygen-containing precursor to a processing region of a semiconductor processing chamber. The methods may include forming a plasma of the oxygen-containing precursor to produce oxygen-containing plasma effluents. The methods may include contacting a substrate housed in the processing region with the oxygen-containing plasma effluents. The substrate may include a boron-and-nitrogen-containing material overlying a carbon-containing material. The boron-and-nitrogen-containing material comprises a plurality of openings. The methods may include etching the carbon-containing material.

The present invention involves a power device and a manufacturing method thereof. The method comprising steps of providing a semiconductor substrate, growing an epitaxial layer on the semiconductor substrate, forming an insulating layer on the epitaxial layer, forming a metal mask layer on the insulating layer, and performing an ion implantation process from above the metal mask layer on the epitaxial layer. The metal mask layer includes an ion implantation blocking region and an ion implantation penetration region.

A method for manufacturing raised strip-shaped active areas is disclosed, including: step 1: performing etching on a semiconductor substrate to form patterning raised strip-shaped structures and shallow trenches; step 2: forming a second dielectric layer which fills the shallow trenches and extends to a surface of the first hard mask layer on top surfaces of the raised strip-shaped structures; step 3: performing the first CMP on second dielectric layer, the first CMP stops at a surface of a first hard mask layer; step 4: performing planarization adjustment on a top surface of the second dielectric layer through second wet etching to reduce a height difference of the top surface of the second dielectric layer in different areas; step 5: removing the first hard mask layer; and step 6: performing third dry etching to reduce the top surface of the second dielectric layer to below the top surface of each raised strip-shaped structure.

A method includes etching a first recess adjacent a first dummy gate stack and a first fin; etching a second recess adjacent a second dummy gate stack and a second fin; and epitaxially growing a first epitaxy region in the first recess. The method further includes depositing a first metal-comprising mask over the first dummy gate stack, over the second dummy gate stack, over the first epitaxy region in the first recess, and in the second recess; patterning the first metal-comprising mask to expose the first dummy gate stack and the first epitaxy region; epitaxially growing a second epitaxy region in the first recess over the first epitaxy region; and after epitaxially growing the second epitaxy region, removing remaining portions of the first metal-comprising mask.

A method of manufacturing a semiconductor device includes the following steps. A photoresist layer is formed over a material layer on a substrate. The photoresist layer is exposed. An organic treatment is performed to the photoresist layer by a hydrophobic organic compound. After performing the organic treatment, the photoresist layer is developed. The material layer is etched using the photoresist layer as a mask.

A method of manufacturing a semiconductor device includes depositing a dielectric layer over a substrate, performing a first patterning to form an opening in the dielectric layer, and depositing an oxide film over and contacting the dielectric layer and within the opening in the dielectric layer. The oxide film is formed from multiple precursors that are free of O.sub.2, and depositing the oxide film includes forming a plasma of a first precursor of the multiple precursors.

A method of forming a semiconductor device that includes forming a hard mask layer on exterior surfaces of a stack of nanostructure layers, in which the hard mask layer including a dielectric base material and a protective oxide surface. A dummy gate is formed on the hard mask layer. A gate sidewall spacer is formed abutting the dummy gate. Source/drain regions are formed. The dummy gate is removed. A first set of the stack of nanostructure layers is removed selectively to a second set of the set of nanostructure layers. The second set of nanostructure layers provides suspended channel regions supported by an inner spacer. A damage path blocking portion of at least the dielectric base material of the hard mask layer is present between the inner spacer and the gate sidewall spacer.

Semiconductor devices and methods of manufacturing the same are described. A silicon wafer is provided and an etch stop bilayer is formed on the silicon wafer. The insertion of an etch stop bilayer in the starting wafer will serve as an etch stop for deep trench formation on the wafer frontside and for wafer backside planarization. With this approach variations in the sacrificial material depth in a GAA device and substrate thickness may offer benefits in lithography overlay control.