An electronic package is provided. The electronic package includes an electronic component and a leadframe. The electronic component has a passive surface. The leadframe includes a first patterned part under the electronic component and configured to provide a power to the electronic component by the passive surface.

A method for manufacturing a semiconductor package includes: providing a leadframe having component positions each of which includes a die pad; providing semiconductor dies each having a first power electrode on a first main surface and a second power electrode on a second main surface; mounting a respective semiconductor die onto the die pad of a respective component position of the leadframe such that the first power electrode is attached to the die pad; mounting a clip onto the dies such that the clip is attached to a respective second power electrode; embedding at least the side faces of the dies and inner surfaces of the leadframe and clip in a mold compound to form a subassembly; and cutting through the clip and leadframe at positions between neighbouring component positions.

Semiconductor device includes: semiconductor elements electrically connected in parallel; pad portion electrically connected to the semiconductor elements; and terminal portion electrically connected to the pad portion. As viewed in thickness direction, the semiconductor elements are aligned along first direction perpendicular to the thickness direction. The pad portion includes closed region surrounded by three line segments each formed by connecting two of first, second and third vertex not disposed on the same straight line. As viewed in thickness direction, the first vertex overlaps with one semiconductor element located in outermost position in first sense of the first direction. As viewed in the thickness direction, the second vertex overlaps with one semiconductor element located in outermost position in second sense of the first direction. As viewed in the thickness direction, the third vertex is located on perpendicular bisector of the line segment connecting the first and second vertex.

Implementations of a semiconductor package may include two or more die, each of the two more die coupled to a metal layer at a drain of each of the two more die, the two or more die and each metal layer arranged in two parallel planes; a first interconnect layer coupled at a source of each of the two more die; a second interconnect layer coupled to a gate of each of the two or more die and to a gate package contact through one or more vias; and an encapsulant that encapsulates the two or more die and at least a portion of the first interconnect layer, each metal layer, and the second interconnect layer.

This insulating chip comprises: an insulating layer; a first coil and a second coil disposed in the insulating layer; and a second electrode electrically connected to the second coil. The second coil has an annular shape in a plan view as seen from the Z direction. The second electrode includes a second inner electrode that is disposed, when viewed in the plan view, over both an inner region surrounded by the second coil and a region overlapping the second coil. A passivation film formed on the upper surface of the insulating layer includes a second inner opening that exposes at least a portion of the second inner electrode. The second inner opening is formed at a position that is over the second inner electrode, and is over both the inner region and the region overlapping the second coil.

The present disclosure provides an ideal diode chip, including a first pin and a second pin arranged on a packaging frame. A power transistor and a first substrate are arranged on the first pin, and a switch transistor and a control module are arranged on the first substrate. The first pin serves as a cathode of the ideal diode chip, and the second pin serves as an anode of the ideal diode chip. The ideal diode chip according to the present disclosure can meet application requirements of different high voltage scenarios.

A semiconductor device has a leadframe and a first electrical component disposed over the leadframe. A clip bond is disposed over the first electrical component. The clip bond has a plurality of recesses each having a different depth. A first recess is proximate to a first distal end of the first electrical component, and a second recess is proximate to a second distal end of the first electrical component opposite the first distal end of the first electrical component. A depth of the first recess is different from a depth of the second recess. A third recess is over a surface of the first electrical component. A depth of the third recess is different from the depth of the first recess and the depth of the second recess. A second electrical component is disposed over the leadframe. The clip bond extends over the second electrical component.

An encapsulation of laser direct structuring (LDS) material is molded onto a substrate having first and second semiconductor dice arranged thereon. Laser beam energy is applied to a surface of the encapsulation of LDS material to structure therein die vias extending through the LDS material to the first and second semiconductor dice and a die-to-die line extending at surface of the LDS material between die vias. Laser-induced forward transfer (LIFT) processing is applied to transfer electrically conductive material to the die vias and the die-to-die line extending between die vias. A layer of electrically conductive material electroless grown onto the die vias and the die-to-die line facilitates improved adhesion of the electrically conductive material transferred via LIFT processing.

According to one embodiment, a semiconductor device includes: a first frame; a first chip on the first frame; a second frame spaced apart from the first frame in a first direction; a second chip on the second frame; and a first joint terminal above the second chip. The first frame includes a first terminal portion extending toward the second frame. The first joint terminal includes a second terminal portion extending toward the first frame. The second terminal portion includes first and second projecting portions each of which projects toward the first frame and which are spaced apart from each other in a second direction. An end portion of the first projecting portion and an end portion of the second projecting portion are each joined on the first terminal portion.

A lead frame according to the present embodiments includes: a main body portion having a main surface including a mounting region on which a semiconductor chip is to be mounted; a lead portion connected to the main body portion; a groove portion provided in a main surface of the main body portion so as to surround the mounting region, the groove portion having an inner side surface and an outer side surface; and a protruding portion protrudingly provided along an inner edge of the groove portion.