An embodiment method includes: forming fins extending from a semiconductor substrate; depositing an inter-layer dielectric (ILD) layer on the fins; forming masking layers on the ILD layer; forming a cut mask on the masking layers, the cut mask including a first dielectric material, the cut mask having first openings exposing the masking layers, each of the first openings surrounded on all sides by the first dielectric material; forming a line mask on the cut mask and in the first openings, the line mask having slot openings, the slot openings exposing portions of the cut mask and portions of the masking layers, the slot openings being strips extending perpendicular to the fins; patterning the masking layers by etching the portions of the masking layers exposed by the first openings and the slot openings; and etching contact openings in the ILD layer using the patterned masking layers as an etching mask.

An exemplary semiconductor structure includes a semiconductor substrate; a plurality of metal lines on top of the semiconductor substrate, each line having a line width 5 nanometers or less: a plurality of dielectric features adjacent to the metal lines; and a plurality of metal vias on top of the metal lines. Out of a random sample of 1000 vias at least 950 vias are fully-aligned to corresponding metal lines.

A method for manufacturing a semiconductor device is provided. The method includes the following. A substrate is provided. A stacked structure is formed on the substrate. The stacked structure includes first material layers and gate layers that are alternatively stacked. The stacked structure includes a giant block (GB) region and a stair-step region. A third material layer is formed on an upper surface of the GB region and an upper surface of the stair-step region. A fourth material layer filling the stair-step region and covering the GB region is formed. At least one contact structure is located in the stair-step region. Each of the at least one contact structure penetrates the third material layer and is connected with a respective one of the gate layers.

An integrated circuit structure includes a first interconnect layer including a first dielectric material. The first dielectric material has a first recess therein, the first recess having a first opening. The integrated circuit structure further includes a second interconnect layer above the first interconnect layer. The second interconnect layer includes a second dielectric material that has a second recess therein. The second recess has a second opening. In an example, at least a portion of the first opening of the first recess abuts and overlaps with at least a portion of the second opening of the second recess. In an example, a continuous conformal layer is on walls of the first and second recesses, and a continuous body of conductive material is within the first and second recesses.

A process includes forming, over a dielectric layer, a hardmask stack including a first layer below a second layer below a third layer below a fourth layer. The first and third layers include a different hardmask material from the second and fourth layers. A trench pattern including sidewall spacer structures is formed over the hardmask stack. The fourth layer is etched in a first region. The fourth and third layers are etched in a second region. The fourth and third layers are etched in a third region. The fourth layer is etched in a fourth region. The second and first layers are etched in the second and third regions. The third layer is etched in the first and fourth regions. In the dielectric layer, trenches are formed in the first and fourth regions, and via openings, deeper than the trenches, are formed in the second and third regions.

A semiconductor structure is disclosed that includes: a source feature and a drain feature disposed in a substrate; a gate structure disposed above the substrate and between the source feature and the drain feature; and a first ladder shallow trench isolation (STI) feature disposed in the substrate at least partially under the gate structure in a channel region between the source feature and the drain feature, the first ladder STI feature including a plurality of sections of different depths including a first depth section and a second depth section.

A semiconductor device includes a conductive feature part, a dielectric structure and a metal layer. The dielectric structure is formed over the conductive feature part. The dielectric structure includes a first dielectric layer and a second dielectric layer stacked on each other. The first dielectric layer and the second dielectric layer include different dielectric materials. The metal layer is disposed in the first dielectric layer and the second dielectric layer. The bottom surface of the metal layer is electrically connected to the conductive feature part, and the top surface of the metal layer is coplanar with the top surface of the dielectric structure. The bottom surface and the top surface of the metal layer have profiles of different sizes.

Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a fin. An insulating structure is directly adjacent sidewalls of the lower fin portion of the fin. A first gate electrode is over the upper fin portion and over a first portion of the insulating structure. A second gate electrode is over the upper fin portion and over a second portion of the insulating structure. A first dielectric spacer is along a sidewall of the first gate electrode. A second dielectric spacer is along a sidewall of the second gate electrode, the second dielectric spacer continuous with the first dielectric spacer over a third portion of the insulating structure between the first gate electrode and the second gate electrode.

Memory circuitry comprising strings of memory cells comprises laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers. Channel-material strings of memory cells extend through the insulative tiers and the conductive tiers in a memory-array region. The insulative tiers and the conductive tiers of the laterally-spaced memory blocks extend from the memory-array region into a stair-step region. Individual stairs in the stair-step region comprise one of the conductive tiers. Conductive vias are individually directly against conducting material that is in the one conductive tier in one of the individual stairs. Insulator material in the stair-step region is directly above the stairs. An insulative-material lining is circumferentially around and extends elevationally along individual of the conductive vias between the individual conductive vias and the insulator material. Individual of the insulative-material linings and the insulator material comprise an interface there-between. Other embodiments, including methods, are disclosed.

Three-dimensional (3D) NAND memory devices and methods are provided. In one aspect, a fabrication method includes forming a conductor/insulator stack over a substrate, configuring memory cells through the conductor/insulator stack, forming a conductive layer, removing a portion of the conductive layer to form an opening in the conductive layer, depositing a dielectric material in a space of the opening, and forming an airgap in the space.