Various embodiments of the present disclosure provide a semiconductor device structure. The semiconductor device structure comprises a substrate comprising a first trench, wherein the first trench extends into a front side surface of the substrate, a first trench capacitor comprising a plurality of first capacitor electrode layers and a plurality of first capacitor dielectric layers disposed in alternating manner within the first trench and over the front side surface of the substrate, wherein a first air gap is enclosed by the plurality of first capacitor electrode layers and the plurality of first capacitor dielectric layers within the first trench, an interconnect structure disposed over the first trench capacitor, wherein one or more first capacitor electrode layers of the plurality of first capacitor electrode layers are in electrical connection with a first conductive feature in a dielectric layer of the interconnect structure, and a first seal ring structure disposed in the interconnect structure and encircling an interior portion of the substrate, wherein at least a portion of the first seal ring structure is in contact with the first conductive feature.

Various embodiments of stacked structures, process steps and methods are provided herein for etching high aspect ratio features (e.g., features having an aspect ratio 30:1) within stacked structures to reduce or eliminate problems that occur during conventional HAR etch processes. More specifically, novel hard mask layers and methods are provided to improve the etch profile, post-etch surface roughness and CD uniformity of high aspect ratio features etched within hard mask layers, as well as the etch selectivity to layer(s) underlying the hard mask layers or other semiconductor materials exposed on the substrate surface.

Provided are a gate contact structure and a method of manufacturing the gate contact structure. The gate contact structure includes a gate electrode, an etch stop layer provided on the gate electrode, a capping layer provided on the etch stop layer, a contact hole including a first portion provided in the etch stop layer and coming in contact with the gate electrode and a second portion provided in the capping layer and communicating with the first portion, and a gate contact plug provided in the contact hole. A width of the first portion is greater than a width of the second portion.

Representative implementations provide techniques for processing integrated circuit (IC) dies and related devices, in preparation for stacking and bonding the devices. The disclosed techniques provide removal of processing residue from the device surfaces while protecting the underlying layers. One or more sacrificial layers may be applied to a surface of the device during processing to protect the underlying layers. Processing residue is attached to the sacrificial layers instead of the device, and can be removed with the sacrificial layers.

The present disclosure provides a method of manufacturing a semiconductor structure. A substrate is provided. A multi-layer structure is formed over the substrate, wherein the multi-layer structure includes a semiconductive material layer and an oxide layer over the semiconductive material layer. The oxide layer is patterned to form a first patterned layer. A second patterned layer is formed on the semiconductive material layer and alternately arranged with the first patterned layer. A first etching operation is performed on the substrate using a comprehensive pattern of the first patterned layer and the second patterned layer.

The present disclosure provides one embodiment of a method of forming an integrated circuit structure. The method includes forming a shallow trench isolation (STI) structure in a semiconductor substrate of a first semiconductor material, thereby defining a plurality of fin-type active regions separated from each other by the STI structure; forming gate stacks on the fin-type active regions; forming an inter-layer dielectric (ILD) layer filling in gaps between the gate stacks; patterning the ILD layer to form a trench between adjacent two of the gate stacks; depositing a first dielectric material layer that is conformal in the trench; filling the trench with a second dielectric material layer; patterning the second dielectric material layer to form a contact opening; and filling a conductive material in the contact opening to form a contact feature.

The present disclosure provides a method of fabricating a semiconductor device. The method includes forming a first interconnect layer over a substrate, the first interconnect layer including a first conductive feature and a second conductive feature, forming a patterned mask on the first interconnect layer, one or more openings in the patterned mask overlaying the second conductive feature, recessing the second conductive feature through the one or more openings in the patterned mask, and forming a second interconnect layer over the first interconnect layer. The second interconnect layer includes a first via in contact with the first conductive feature and a second via in contact with the second conductive feature.

Methods of forming high aspect ratio openings. The method comprises removing a portion of a dielectric material at a temperature less than about 0 C. to form at least one opening in the dielectric material. The at least one opening comprises an aspect ratio of greater than about 30:1. A protective material is formed in the at least one opening and on sidewalls of the dielectric material at a temperature less than about 0 C. Methods of forming high aspect ratio features are also disclosed, as are semiconductor devices.

A conductive interconnection structure includes a conductive feature part, a dielectric structure, a trench filling portion, a via portion and a metal layer. The dielectric structure is formed over the conductive feature part. The dielectric structure includes a first dielectric layer and a second dielectric layer stacked on each other. The second dielectric layer covers the first dielectric layer. The trench filling portion is embedded in the dielectric structure, and the trench filling portion and the second dielectric layer have different etching selectivities. The via portion is located in the first dielectric layer at the bottom surface of the trench filling portion. The metal layer penetrates the dielectric structure, the trench filling portion and the via portion, and the bottom surface of the metal layer is electrically connected to the conductive feature part.

A method for manufacturing a semiconductor device includes forming a conductive feature in a first dielectric layer; forming a second dielectric layer on the first dielectric layer; forming a trench that penetrates through the second dielectric layer, and terminates at the conductive feature; forming a contact layer in the trench and on the conductive feature; etching back the contact layer to form a first via contact feature in the trench, the first via contact feature being electrically connected to the conductive feature; and forming a second via contact feature on the first via contact feature in the trench.