Some implementations described herein a provide a multi-die package and methods of formation. The multi-die package includes a dynamic random access memory integrated circuit die over a system-on-chip integrated circuit die, and a heat transfer component between the system-on-chip integrated circuit die and the dynamic random access memory integrated circuit die. The heat transfer component, which may correspond to a dome-shaped structure, may be on a surface of the system-on-chip integrated circuit die and enveloped by an underfill material between the system-on-chip integrated circuit die and the dynamic random access memory integrated circuit die. The heat transfer component, in combination with the underfill material, may be a portion of a thermal circuit having one or more thermal conductivity properties to quickly spread and transfer heat within the multi-die package so that a temperature of the system-on-chip integrated circuit die satisfies a threshold.

A back grinding adhesive film used to protect a surface of a wafer, the back grinding adhesive film including a base material layer, and an adhesive resin layer which is formed on one surface side of the base material layer and configured with an ultraviolet curable adhesive resin material, in which, when a viscoelastic characteristic is measured after curing the ultraviolet curable adhesive resin material by irradiating with an ultraviolet ray, a storage elastic modulus at 5 C. E (5 C.) is 2.010.sup.6 to 2.010.sup.9 Pa, and a storage elastic modulus 100 C. E (100 C.) is 1.010.sup.6 to 3.010.sup.7 Pa.

A wafer processing method includes emitting a laser beam along an annular line that is a predetermined distance inward of the outer circumferential edge of the first wafer to form, in the first wafer, an annular first modified layer and a first crack extending from the first modified layer to make an appearance on the front surface, thereby causing the first wafer to become warped at an outer circumferential region thereof that lies closer to the outer circumferential edge than does the first modified layer and the first crack; bonding the front surface of the first wafer to a second wafer to form a bonded wafer stack; and grinding a rear surface of the first wafer of the bonded wafer stack to thin the first wafer to a finish thickness.

An expansion method includes an expansion step of expanding a sheet between an outer periphery of a wafer and an inner periphery of an annular frame in a wafer unit, and a heating step of heating the sheet in its region between the outer periphery of the wafer and the inner periphery of the annular frame by a heating unit to allow slack of the sheet, the slack having been formed in the expansion step, to shrink. The region includes a first region, and a second region that is harder to shrink by the heating than the first region. On the sheet, heat spots of a temperature higher than that of the sheet surrounding the heat spots are formed with heat radiated to the sheet. In the heating step, the heating unit is moved such that the heat spots are positioned over an entirety of at least the second region.

A wafer-level-package device with peripheral side wall protection has a die, multiple conductive bumps, and a protection layer. The die has a top surface, a bottom surface, and a peripheral side wall. A cavity is formed on the peripheral side wall of the die and around the die. The multiple conductive bumps are mounted on at least one of the top surface and the bottom surface of the die. The protection layer covers the die, the cavity, and the multiple conductive bumps. The multiple conductive bumps are exposed from the protection layer.

A semiconductor device includes a semiconductor layer that includes a semiconductor substrate having a first thickness and has a main surface, a main surface electrode that is arranged at the main surface and has a second thickness less than the first thickness, and a pad electrode that is arranged on the main surface electrode and has a third thickness exceeding the first thickness.

A die attach film structure includes a dicing film, an insulating adhesion layer including an upper surface and a lower surface opposite the upper surface, the lower surface of the insulating adhesion layer contacting an upper surface of the dicing film and including an insulating filler, and a conductive adhesion layer contacting an upper surface of the insulating adhesion layer and including a conductive filler.

A semiconductor package includes a semiconductor die, a redistribution circuit structure, a supporting structure and a protective layer. The redistribution circuit structure is located on and electrically coupled to the semiconductor die. The supporting structure is located on an outer surface of the redistribution circuit structure, wherein the supporting structure is overlapped with at least a part of the semiconductor die or has a sidewall substantially aligned with a sidewall of the semiconductor die in a vertical projection on the redistribution circuit structure along a stacking direction of the redistribution circuit structure and the supporting structure. The protective layer is located on the supporting structure, wherein the supporting structure is sandwiched between the protective layer and the redistribution circuit structure.

The present disclosure provides a method for manufacturing a semiconductor package. The method includes disposing a first semiconductor substrate on a temporary carrier and dicing the first semiconductor substrate to form a plurality of dies. Each of the plurality of dies has an active surface and a backside surface opposite to the active surface. The backside surface is in contact with the temporary carrier and the active surface faces downward. The method also includes transferring one of the plurality of dies from the temporary carrier to a temporary holder. The temporary holder only contacts a periphery portion of the active surface of the one of the plurality of dies.

Semiconductor processing methods and apparatuses are provided. Some methods include providing a first wafer to a processing chamber, the first wafer having a thickness, a beveled edge, a first side, and a plurality of devices formed in a device area on the first side, the device area having an outer perimeter, depositing an annular ring of material on the first wafer, the annular ring of material covering a region of the beveled edge and the outer perimeter of the device area, and having an inner boundary closer to the center point of the first wafer than the outer perimeter, bonding a second substrate to the plurality of devices and to a portion of the annular ring of material, and thinning the thickness of the first wafer.