H10P72/7422

Wafer processing method
12519019 · 2026-01-06 · ·

A wafer processing method includes forming a start point of division along division lines, providing, on a front surface of the wafer, a protective member for protecting the front surface of the wafer, grinding a back surface of the wafer to a desired thickness, forming division grooves in the division lines to divide the wafer into individual device chips, providing an expandable sheet to the back surface of the wafer and removing the protective member from the front surface of the wafer, coating the front surface of the wafer with an adhesive liquid having flowability, expanding and shrinking the sheet so as to allow the adhesive liquid to enter each of the division grooves and to discharge the adhesive liquid from the division grooves, and removing the adhesive liquid from the front surface of the wafer to clean a side surface of each of the division grooves.

CHIP MANUFACTURING METHOD
20260011562 · 2026-01-08 ·

A chip manufacturing method includes: preparing a wafer unit having a protective member fixed to one surface of a wafer and having a recess and a loop-shaped protrusion surrounding the recess on the other surface side of the wafer, the protective member including a first sheet in contact with the wafer, a resin layer stacked on the first sheet, and a second sheet stacked on the resin layer; processing the wafer and the protective member along a boundary between the recess and the loop-shaped protrusion to separate the recess and the loop-shaped protrusion from each other; and after separating of the recess and the loop-shaped protrusion, holding the protective member side of the wafer on a holding table and dividing the wafer from the other surface side to manufacture a plurality of chips.

Polysiloxane-containing temporary adhesive comprising heat-resistant polymerization inhibitor

A temporary adhesive without the formation of voids between a support and a wafer. A temporary adhesive for separatably attaching a support to a circuit side of a wafer to process a rear surface of the wafer, the temporary adhesive including a component (A) that is cured by a hydrosilylation reaction; a polymerization inhibitor (B) having a 5% mass decrease temperature of 80 C. or higher as measured using a Tg-DTA; and a solvent (C). The component (A) may include a polysiloxane (A1) including a polyorganosiloxane (a1) containing a C.sub.1-10 alkyl group and a C.sub.2-10 alkenyl group, and a polyorganosiloxane (a2) containing a C.sub.1-10 alkyl group and a hydrogen atom; and a platinum group metal-based catalyst (A2). The polymerization inhibitor (B) may be a compound of formula (1): ##STR00001##
(wherein R.sup.7 and R.sup.8 are each a C.sub.6-40 aryl group, or a combination of a C.sub.1-10 alkyl group and a C.sub.6-40 aryl group).

Bonded structures without intervening adhesive

A bonded structure can include a first reconstituted element comprising a first element and having a first side comprising a first bonding surface and a second side opposite the first side. The first reconstituted element can comprise a first protective material disposed about a first sidewall surface of the first element. The bonded structure can comprise a second reconstituted element comprising a second element and having a first side comprising a second bonding surface and a second side opposite the first side. The first reconstituted element can comprise a second protective material disposed about a second sidewall surface of the second element. The second bonding surface of the first side of the second reconstituted element can be directly bonded to the first bonding surface of the first side of the first reconstituted element without an intervening adhesive along a bonding interface.

Tape sticking system, tape sticking method, tape peeling system, and tape peeling method

The present invention relates to a tape sticking system for sticking a protective tape for protecting a peripheral portion of a substrate, such as a wafer. The tape sticking apparatus (10) includes a substrate holder (21) for sticking, a side roller (43), a first roller (46), a second roller (47), a roller-driving motor (49) coupled to the second roller (47), and a nipping mechanism (60) for nipping the peripheral portion of the substrate (W) with the first roller (46) and the second roller (47). The tape sticking apparatus (10) is configured to cause the second roller (47) to be rotated by use of the roller-driving motor (49) while nipping the peripheral portion of the substrate, held to the substrate holder (21) for sticking, with the first roller (46) and the second roller (47), to thereby rotate the substrate.

Silicon fragment defect reduction in grinding process

A method is provided for fabricating a semiconductor wafer having a device side, a back side opposite the device side and an outer periphery edge. Suitably, the method includes: forming a top conducting layer on the device side of the semiconductor wafer; forming a passivation layer over the top conducting layer, the passivation layer being formed so as not to extend to the outer periphery edge of the semiconductor wafer; and forming a protective layer over the passivation layer, the protective layer being spin coated over the passivation layer so as to have a smooth top surface at least in a region proximate to the outer periphery edge of the semiconductor wafer.

Back grinding adhesive film and method for manufacturing electronic device

A back grinding adhesive film used to protect a surface of a wafer, the back grinding adhesive film including a base material layer, and an adhesive resin layer which is formed on one surface side of the base material layer and configured with an ultraviolet curable adhesive resin material, in which, when a viscoelastic characteristic is measured after curing the ultraviolet curable adhesive resin material by irradiating with an ultraviolet ray, a storage elastic modulus at 5 C. E (5 C.) is 2.010.sup.6 to 2.010.sup.9 Pa, and a storage elastic modulus 100 C. E (100 C.) is 1.010.sup.6 to 3.010.sup.7 Pa.

SEMICONDUCTOR DEVICE
20260047478 · 2026-02-12 · ·

A semiconductor device includes a semiconductor layer that includes a semiconductor substrate having a first thickness and has a main surface, a main surface electrode that is arranged at the main surface and has a second thickness less than the first thickness, and a pad electrode that is arranged on the main surface electrode and has a third thickness exceeding the first thickness.

Method of manufacturing semiconductor device

A method of manufacturing a semiconductor device having first and second main surfaces opposite to each other. The method includes: forming a first electrode at the first main surface of the semiconductor wafer; applying a first tape to the second main surface of the semiconductor wafer; forming roughness at a portion of a surface of the first tape; applying a second tape to an outer peripheral portion of the semiconductor wafer, so as to cover the portion of the surface of the first tape, with the roughness formed thereon, at the second main surface of the semiconductor wafer, to cover a portion of the first main surface of the semiconductor wafer, and to cover a side surface of the semiconductor wafer; heating the semiconductor wafer after the first and second tapes are applied; and subsequently forming a plated film at the surface of the first electrode by a plating treatment.

3D SEMICONDUCTOR DEVICES AND STRUCTURES WITH TRANSISTORS, METAL LAYERS, AND SINGLE CRYSTAL TRANSISTOR CHANNELS
20260040578 · 2026-02-05 · ·

A semiconductor device including: a first level including a plurality of first metal layers; a second level overlaying the first level, where the second level includes at least one single-crystal silicon layer and a plurality of transistors, where each of the plurality of transistors includes a single-crystal channel, where the second level includes a plurality of second metal layers which includes interconnections between the plurality of transistors, the second level is overlaid by an isolation layer; a connective path from the plurality of transistors to the plurality of first metal layers, where at least one of the plurality of transistors includes a second single-crystal channel overlaying a first single-crystal channel, where each of at least one of the plurality of transistors includes at least a two sided gate, where the first single-crystal channel is self-aligned to the second single-crystal channel being processed following a same lithography step.