A method of forming a semiconductor device includes: forming a conductive pad over and electrically coupled to an interconnect structure, where the interconnect structure is disposed over a substrate and electrically coupled to electrical components formed on the substrate; forming a passivation layer over the conductive pad and the interconnect structure; and forming a sacrificial test structure over the passivation layer and electrically coupled to the conductive pad, where the sacrificial test structure includes a sacrificial pad extending along an upper surface of the passivation layer distal from the substrate, and includes a sacrificial via extending into the passivation layer and contacting the conductive pad.

A method includes forming a trench in a semiconductor layer of a device wafer and depositing a liner on the trench sidewalls. The liner is removed from the trench bottom, and the trench is deepened anisotropically to form an extension fully along the trench, or locally by applying a mask. The semiconductor material is removed outwardly from the extension by etching to create a cavity wider than the trench and below the liner. A space formed by the trench and cavity is filled with electrically conductive material to form a buried interconnect rail comprising a narrow portion in the trench and a wider portion in the cavity. The wider portion can be contacted by a TSV connection, enabling a contact area between the connection and buried rail. The etching forms a wider rail portion at a location remote from active devices formed on the front surface of the semiconductor layer.

A semiconductor device and a manufacturing method therefor are disclosed, in which a first opening is formed in a first metal layer by etching away part of the first metal layer, and a second metal layer is filled in the first opening and is electrically connected to the remainder of the first metal layer. A TSV extends sequentially through a substrate and a partial thickness of a dielectric layer so that the second metal layer is exposed therein, and an interconnect layer in the TSV is electrically connected to the second metal layer. In this way, the first metal layer can be picked up as long as projections of the second metal layer and the interconnect layer on the substrate are encompassed within a projection of the first metal layer on the substrate, without any additional lateral area of the first metal layer being occupied by the TSV.

A circuit device includes: a first substrate having a first barrier layer; a second substrate having a second barrier layer; a first conductive portion arranged over the first barrier layer; a second conductive portion arranged over the second barrier layer; a first expanding pad arranged on the first conductive portion and including a first contact area greater than that of the first conductive portion; and a second expanding pad bonded to the first expanding pad, arranged on the second conductive portion and including a second expanded contact area greater than that of the second conductive portion. The first barrier layer and the second barrier layer include aluminum fluoride.

A method of manufacturing a semiconductor package includes providing a wafer substrate including a first a chip area and an edge area; forming first and second conductive layers on the wafer substrate; forming a photoresist pattern, including openings, on the second conductive layer, wherein the photoresist pattern includes a first photoresist pattern on the chip area and a second photoresist pattern on the edge area; forming conductive patterns within the openings; removing the first photoresist pattern from the photoresist pattern, and portions of the first and second conductive layers overlapping with the first photoresist pattern; removing the second photoresist pattern from the photoresist pattern, and a portion of the second conductive layer overlapping the second photoresist pattern, such that a portion of the first conductive layer on the edge area is exposed; and forming a protective film such that the protective film is on the conductive patterns.

A wafer stacking method and a wafer stack structure are disclosed. In the wafer stacking method, first and second wafer structures are formed and then stacked and bonded. Prior to the stacking and bonding of the first and second wafer structures, metal pad is pre-formed on one side of the first wafer structure. In this way, it is unnecessary to form the metal pad after the first and second wafer structures are stacked and bonded, avoiding wafer warpage distortion, which may occur in high-temperature treatment involved in the formation of the metal pad. Thus, the risks of layer and/or film fracture and alarming of processing equipment in subsequent processes are reduced, and more wafers are allowed to be stacked by wafer-level stacking. The wafer stack structure is obtainable according to the wafer stacking method.

A method according to the present disclosure includes providing a first workpiece that includes a first substrate and a first interconnect structure, providing a second workpiece that includes a second substrate, a second interconnect structure, and a through via extending through a portion of the second substrate and a portion of the second interconnect structure, forming a first bonding layer on the first interconnect structure, forming a second bonding layer on the second interconnect structure, bonding the second workpiece to the first workpiece by directly bonding the second bonding layer to the first bonding layer, thinning the second substrate, forming a protective film over the thinned second substrate, forming a backside via opening through the protective film and the thinned second substrate to expose the through via, and forming a backside through via in the backside via opening to physically couple to the through via.

Representative techniques and devices including process steps may be employed to mitigate the potential for delamination of bonded microelectronic substrates due to metal expansion at a bonding interface. For example, a metal pad having a larger diameter or surface area (e.g., oversized for the application) may be used when a contact pad is positioned over a TSV in one or both substrates.

An IC structure includes a first transistor, a second transistor, a dielectric fin, a dielectric cap, a backside metal structure, and a source/drain contact. The first transistor includes a first channel region, a first gate structure, and first source/drain features disposed on opposite sides of the first gate structure. The second transistor includes a second channel region, a second gate structure, and second source/drain features disposed on opposite sides of the second gate structure. The dielectric fin is disposed between the first and second transistors. The dielectric cap interfaces a backside surface of the dielectric fin. The source/drain contact abuts the dielectric fin and is electrically coupled to a first one of the first source/drain features by way of a silicide layer and electrically coupled to the backside metal rail by way of physical contact established by the source/drain contact and the backside metal rail.

An embodiment semiconductor device may include a semiconductor die; one or more redistribution layers formed on a surface of the semiconductor die and electrically coupled to the semiconductor die; and an active or passive electrical device electrically coupled to the one or more redistribution layers. The active or passive electrical device may include a silicon substrate and a through-silicon-via formed in the silicon substrate. The active or passive electrical device may be configured as an integrated passive device including a deep trench capacitor or as a local silicon interconnect. The semiconductor device may further include a molding material matrix formed on a surface of the one or more redistribution layers such that the molding material matrix partially or completely surrounds the active or passive electrical device.