Stacked devices and methods of fabrication are provided. Die-to-wafer (D2W) direct-bonding techniques join layers of dies of various physical sizes, form factors, and foundry nodes to a semiconductor wafer, to interposers, or to boards and panels, allowing mixing and matching of variegated dies in the fabrication of 3D stacked devices during wafer level packaging (WLP). Molding material fills in lateral spaces between dies to enable fan-out versions of 3D die stacks with fine pitch leads and capability of vertical through-vias throughout. Molding material is planarized to create direct-bonding surfaces between multiple layers of the variegated dies for high interconnect density and reduction of vertical height. Interposers with variegated dies on one or both sides can be created and bonded to wafers. Logic dies and image sensors from different fabrication nodes and different wafer sizes can be stacked during WLP, or logic dies and high bandwidth memory (HBM) of different geometries can be stacked during WLP.

A microelectronic structure is disclosed. The microelectronic structure can include a bulk semiconductor portion that has a first surface and a second surface opposite the first surface. The microelectronic structure can include a via structure that extends at least partially through the bulk semiconductor portion along a direction non-parallel to the first surface. The microelectronic structure can include a first dielectric barrier layer that is disposed on the first surface of the bulk semiconductor portion and extends to the via structure. The microelectronic structure can include a second dielectric layer that is disposed on the first dielectric barrier layer and extends to the via structure.

A microelectronic structure with through substrate vias (TSVs) and method for forming the same is disclosed. The microelectronic structure can include a bulk semiconductor with a via structure. The via structure can have a first and second conductive portion. The via structure can also have a barrier layer between the first conductive portion and the bulk semiconductor. The structure can have a second barrier layer between the first and second conductive portions. The second conductive portion can extend from the second barrier layer to the upper surface of the bulk semiconductor. The microelectronic structure containing TSVs is configured so that the microelectronic structure can be bonded to a second element or structure.

A method includes forming integrated circuits on a front side of a first chip, performing a backside grinding on the first chip to reveal a plurality of through-vias in the first chip, and forming a first bridge structure on a backside of the first chip using a damascene process. The bridge structure has a first bond pad, a second bond pad, and a conductive trace electrically connecting the first bond pad to the second bond pad. The method further includes bonding a second chip and a third chip to the first chip through face-to-back bonding. A third bond pad of the second chip is bonded to the first bond pad of the first chip. A fourth bond pad of the third chip is bonded to the second bond pad of the first chip.

An electronic system includes a first device and a second device bonded to the first device. The first device includes: a semiconductor substrate with an opening; a stack having metal layers and conductive vias; and a conductive layer including aluminum having a first face in contact with the stack and a second face, opposite the first face, that is partially exposed through the opening. The metal layers and the conductive vias of the stack are made of a conductive material different from aluminum.

A back-side ground and power-distribution network is formed on a semiconductor wafer substrate by selectively etching first and second back-side partial-substrate rail (PSR) trench openings through a back-side surface of the wafer substrate, selectively forming a plurality of defined n-type conductive regions and defined p-type conductive regions in the wafer substrate at the bottoms of the first and second back-side PSR trench openings in position for electrical contact with n-well and p-well regions, and then forming first and second back-side PSR conductors in the first and second back-side PSR trench openings to be directly electrically connected over the plurality of defined n-type conductive regions and defined p-type conductive regions to the n-well and p-well regions in the wafer substrate.

A method of manufacturing a device includes forming a conductive film on a second surface of a substrate having a first surface and the second surface opposite to the first surface by using a non-superconducting material, forming a through hole penetrating the substrate by etching the substrate from the first surface after forming the conductive film, forming a through electrode in the through hole by using a superconducting material by an electroplating method using the conductive film exposed in the through hole as a seed layer, and removing the conductive film after forming the through electrode.

A backside power and ground distribution network is formed on a wafer substrate layer by selectively etching backside PSV openings through a backside surface of the wafer substrate layer, forming n-type and p-type conductive regions in the wafer substrate layer at the bottoms of first and second backside PSV openings in position for electrical contact with an n-well and p-well regions, and then forming first and second backside PSV conductors in the first and second backside PSV openings to be directly electrically connected over the n-type and p-type conductive regions to the n-well and p-well regions in the wafer substrate layer.

A quantum computing system that includes a quantum circuit device having at least one operating frequency; a first substrate having a first surface on which the quantum circuit device is disposed; a second substrate having a first surface that defines a recess of the second substrate, the first and second substrates being arranged such that the recess of the second substrate forms an enclosure that houses the quantum circuit device; and an electrically conducting layer that covers at least a portion of the recess of the second substrate.

A semiconductor device comprises a III-N device including an insulating substrate. The insulating substrate includes a first side and a second side. The device further includes a III-N material structure on a first side of the insulating substrate, and a gate electrode, a source electrode, and a drain electrode on a side of the III-N material structure opposite the substrate. A backmetal layer on the second side of the insulating substrate, and a via hole is formed through the III-N material structure and the insulating substrate. A metal formed in the via-hole is electrically connected to the drain electrode on the first side of the substrate and electrically connected to the backmetal layer on the second side of the substrate.