The present disclosure provides a method for forming an integrated circuit (IC) structure. The method comprises providing a substrate including a conductive feature; forming aluminum (Al)-containing dielectric layer on the conductive feature; forming a low-k dielectric layer on the Al-containing dielectric layer; and etching the low-k dielectric layer to form a contact trench aligned with the conductive feature. A bottom of the contact trench is on a surface of the Al-containing dielectric layer.

Metal-insulator-metal (MIM) capacitor, an integrated semiconductor device having a MIM capacitor and methods of making. The MIM capacitor includes a first metal layer, a second metal layer and a dielectric layer located between the second metal layer and the first metal layer. The first metal layer, the second metal layer and the dielectric layer may be formed in a comb structure, wherein the comb structure include a first tine structure and at least a second tine structure.

The present disclosure relates to a method of forming an interconnect structure that eliminates a separate deep via patterning process to simplify the fabrication process. In some embodiments, a first dielectric layer is formed over a first metal line and patterned to form a through-hole exposing a first contact region of the first metal line. A second dielectric layer is deposited and patterned to form a first via-hole connecting to the through-hole and a second via-hole exposing a second contact region of the second metal line from a layout view. A first via is formed on the first contact region extending to a first upper surface of the second dielectric layer, and a second via is formed on the second contact region extending to a second upper surface of the second dielectric layer.

The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate; a first bottom conductive layer positioned in the substrate; a bottom porous dielectric layer positioned on the substrate; a top porous dielectric layer positioned on the bottom porous dielectric layer; a middle porous dielectric layer positioned between the bottom porous dielectric layer and the top porous dielectric layer; and a mixing-area conductive structure positioned along the top porous dielectric layer, the middle porous dielectric layer, and the bottom porous dielectric layer, and positioned on the first bottom conductive layer. A porosity of the top porous dielectric layer is greater than a porosity of the middle porous dielectric layer. The porosity of the middle porous dielectric layer is greater than a porosity of the bottom porous dielectric layer.

A semiconductor structure comprises two or more interconnect lines of a first width in a given interconnect level, and two or more interconnect lines of a second width in the given interconnect level. The two or more interconnect lines of the second width are disposed between a first one of the two or more interconnect lines of the first width and a second one of the two or more interconnect lines of the second width. The two or more interconnect lines of the first width have sidewalls with a negative taper angle. The two or more interconnect lines of the second width have sidewalls with a positive taper angle.

Metallization interconnect structures, integrated circuit devices, and methods related to high aspect ratio interconnects are discussed. A self assembled monolayer is selectively formed on interlayer dielectric sidewalls of an opening that exposes an underlying metallization structure. A first metal is formed on the underlying metallization structure and within only a bottom portion of the self assembled monolayer. The exposed portion of the self assembled monolayer is removed and a second metal is formed over the first metal.

A dielectric structure is formed over a layer than contains a conductive component. An opening is formed in the dielectric structure. The opening exposes an upper surface of the conductive component. A first deposition process is performed that deposits a first conductive layer over the dielectric structure and partially in the opening. A treatment process is performed on a first portion of the first conductive layer formed over the dielectric structure. The treatment process introduces a non-metal material to the first portion of the first conductive layer. After the treatment process has been performed, a second deposition process is performed that at least partially fills the opening with a second conductive layer without trapping a gap therein.

Methods and apparatuses for depositing dielectric films into features on semiconductor substrates are described herein. Methods involve depositing dielectric films by using controlled thermal chemical vapor deposition, with periodic passivation operations and densification to modulate film properties.

An integrated circuit (IC) is described. The IC includes a dielectric layer of a first dielectric material. The IC also includes a first metal layer in the dielectric layer. The first metal layer has a first adhesion layer on a backside surface, a second adhesion layer on a frontside surface of the first metal layer. Additionally, the first metal layer has dielectric alignment structures on the second adhesion layer of a second dielectric material different from the first dielectric material. The IC further includes a second metal layer landing on the second adhesion layer on the frontside surface of the first metal layer, between the dielectric alignment structures.

A semiconductor structure includes a semiconductor fin protruding from a substrate; a gate structure engaging with the semiconductor fin. The semiconductor structure also includes an interlayer dielectric (ILD) layer disposed over the substrate and adjacent to the gate structure, where a top surface of the gate structure is below a top surface of the ILD layer; a first metal layer in direct contact with a top surface of the gate structure; a second metal layer disposed over the first metal layer, where the first metal layer is disposed on bottom and sidewall surfaces of the second metal layer, where the bottom surface of the second metal layer has a concave profile, and where the second metal layer differs from the first metal layer in composition; and a gate contact disposed over the second metal layer.