A method of fabricating a semiconductor device includes providing a substrate structure comprising a semiconductor substrate of a first conductivity type, a drift layer on the semiconductor substrate, and a fin array on the drift layer and surrounded by a recess region. The fin array comprises a first row of fins and a second row of fins parallel to each other and separated from each other by a space. The first row of fins comprises a plurality of first elongated fins extending parallel to each other in a first direction. The second row of fins comprises a plurality of second elongated fins extending parallel to each other in a second direction parallel to the first direction. The method also includes epitaxially regrowing a gate layer surrounding the first and second row of fins on the drift layer and filling the recess region.

An array of semiconductor fins is formed on a top surface of a substrate. A dielectric material liner is formed on the surfaces of the array of semiconductor fins. A photoresist layer is applied and patterned such that sidewalls of an opening in the photoresist layer are parallel to the lengthwise direction of the semiconductor fins, and are asymmetrically laterally offset from a lengthwise direction passing through the center of mass of a semiconductor fin to be subsequently removed. An angled ion implantation is performed to convert a top portion of dielectric material liner into a compound material portion. The compound material portion is removed selective to the remaining dielectric material liner, and the physically exposed semiconductor fin can be removed by an etch or converted into a dielectric material portion by a conversion process. The dielectric material liner can be removed after removal of the semiconductor fin.

A device including an activated p-type layer comprising a III-Nitride based Mg-doped layer grown by vapor phase deposition or a growth method different from MBE. The p-type layer is activated through a sidewall of the p-type layer after the removal of defects from the sidewall thereby increasing a hole concentration in the p-type layer. In one or more examples, the device includes an active region between a first n-type layer and the p-type layer; a second n-type layer on the p-type layer; and a tunnel junction between the second n-type layer and the p-type layer, and the activated p-type layer has a hole concentration characterized by a current density of at least 100 Amps per centimeter square flowing between the first n-type layer and the second n-type layer in response to a voltage of 4 volts or less applied across the first n-type layer and the second n-type layer.