Patent classifications
H10P50/242
Systems and methods for processing a silicon surface using multiple radical species
A method of processing a silicon surface includes using a first radical species to remove contamination from the surface and to roughen the surface; and using a second radical species to smooth the roughened surface. Reaction systems for performing such a method, and silicon surfaces prepared using such a method, also are provided.
Semiconductor device and method for manufacturing semiconductor device
A method for manufacturing a semiconductor device includes forming a first insulating layer on a first nitride semiconductor layer having a principal surface, forming a mask including a first mask opening on the first insulating layer, forming a first opening in the first insulating layer through the first mask opening, forming a second nitride semiconductor layer on the first nitride semiconductor layer inside the first opening, forming a second insulating layer covering a boundary between the second nitride semiconductor layer and the first insulating layer through the first mask opening and thereafter removing the mask, forming a second opening in the second insulating layer, forming a first electrode on the second insulating layer contacting the second nitride semiconductor layer through the second opening, and forming a gate electrode above the first nitride semiconductor layer, and separated from the second insulating layer in a plan view perpendicular to the principal surface.
Arcing reduction in wafer bevel edge plasma processing
Methods and systems for processing a bevel edge of a wafer in a bevel plasma chamber. The method includes receiving a pulsed mode setting for a RF generator of the bevel plasma chamber. The method includes identifying a duty cycle for the pulsed mode, the duty cycle defining an ON time and an OFF time during each cycle of power delivered by the generator. The method includes calculating or accessing a compensation factor to an input RF power setting of the generator. The compensation factor is configured to add an incremental amount of power to the input power setting to account for a loss in power attributed to the duty cycle to be run in the pulsed mode. The method is configured to run the generator in the pulse mode with the duty cycle and the pulsing frequency. The generator is configured to generate the input power in pulsing mode that includes incremental amount of power to achieve an effective power in the bevel plasma chamber to achieve a target bevel processing throughput, while reducing charge build-up that causes arcing damage.
Laser induced semiconductor wafer patterning
A semiconductor wafer processing method, having: ablating a back side of a semiconductor wafer with a laser ablation process; and etching the back side of the semiconductor wafer with an etching process; wherein the laser ablation process forms a pattern in the back side of the semiconductor wafer; wherein the etching process preserves the pattern in the back side of the semiconductor wafer.
SEMICONDUCTOR VAPOR ETCHING DEVICE WITH INTERMEDIATE CHAMBER
A semiconductor vapor etching device is disclosed. The device can include an intermediate chamber between a vapor source and a reaction chamber. Etch reactant vapor can be pulsed from the intermediate chamber to the reaction chamber to etch a substrate.
ETCHING METHOD, METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, NONTRANSITORY COMPUTER-READABLE RECORDING MEDIUM AND PROCESSING APPARATUS
An etching technique removes a film by supplying a first gas containing a first halogen element and a second gas containing a second halogen element. In embodiments, the first gas includes a Group 13 halide and the second gas includes a chlorine-containing compound with a Group 16 element. The gases are introduced with different start times, optionally with a period of simultaneous supply, so the first gas weakens bonds in a nitride or oxide and the second gas accelerates removal. The method suits cleaning deposits from internal surfaces of a process vessel and etching films on a substrate. After etching, a cyclic purge removes residual species. A pre-coating step may form a nitride film to suppress diffusion of elements and stabilize initial film growth.
APPARATUS AND METHOD FOR ATOMIC LAYER ETCHING BASED ON CONTROL OF CHARGED PARTICLES
Provided is an atomic layer etching apparatus comprising: a plasma source; a grid assembly composed of a plurality of grids to which potentials can be applied, disposed at the front of the plasma source, and configured to extract charged particles from the plasma; and a magnetic field applying module configured to apply a magnetic field to a flight space of the charged particles so that the charged particles are obliquely incident on a target substrate at a preset angle. The charged particles extracted from the plasma by the grid assembly fly while rotating with a preset curvature by the magnetic field and are obliquely incident on the substrate. As a result, the apparatus limits the collision energy of the charged particles when they are incident on the substrate, thereby enabling atomic layer etching of the target substrate.
Multi-die semiconductor wafer using silicon wafer substrate embedment
A method for fabricating a semiconductor wafer may etch a surface of a silicon substrate to form a first cavity and a second cavity. The method may apply a first dielectric layer to the surface of the silicon substrate, the first cavity, and the second cavity. The method may affix a first die into the first cavity of the silicon substrate. The method may affix a second die into the second cavity of the silicon substrate. The method may apply a second dielectric layer to the surface of the silicon substrate, an exposed surface of the first die, and an exposed surface of the second die. The method may form a redistribution layer over the second dielectric layer, where the redistribution layer is configured to electrically couple the first die to the second die.
Method of manufacturing a structure by asymmetrical ion bombardment of a capped underlying layer
A method of fabricating semiconductor fins, including, patterning a film stack to produce one or more sacrificial mandrels having sidewalls, exposing the sidewall on one side of the one or more sacrificial mandrels to an ion beam to make the exposed sidewall more susceptible to oxidation, oxidizing the opposite sidewalls of the one or more sacrificial mandrels to form a plurality of oxide pillars, removing the one or more sacrificial mandrels, forming spacers on opposite sides of each of the plurality of oxide pillars to produce a spacer pattern, removing the plurality of oxide pillars, and transferring the spacer pattern to the substrate to produce a plurality of fins.
Substrate processing apparatus, substrate processing method, and method of fabricating semiconductor device
A substrate processing apparatus, a substrate processing method, and a method of fabricating a semiconductor device are provided. The substrate processing method includes providing a process gas, generating a preliminary etchant, which includes a first etchant and a second etchant, from the process gas through plasma ignition, generating a process etchant by controlling a composition ratio of the preliminary etchant, and performing a selective etching of the substrate with the process etchant.