A disclosed gas supply system includes a gas supply line and a gas recovery line. The gas supply line supplies a heat transfer gas to a gap between a substrate support and a back surface of a substrate. The gas supply line includes first to third portions and a pressure controller. The second portion extends downstream of the first portion. The pressure controller regulates a pressure of the heat transfer gas and is connected between the first portion and the second portion. The third portion connects the second portion and the gap. The gas recovery line is connected to the first and second portions. The gas recovery line includes a pump connected between the first and the second portions. The gas recovery line shares the third portion with the gas supply line. The gas recovery line returns the heat transfer gas from the second portion to the first portion.

A plasma producing apparatus for plasma processing a substrate Includes a chamber having an interior surface, a plasma production device for producing an inductively coupled plasma within the chamber, a substrate support for supporting the substrate during plasma processing, and a Faraday shield disposed within the chamber for shielding at least part of the interior surface from material removed from the substrate by the plasma processing. The plasma production device includes an antenna and a RF power supply for supplying RF power to the antenna with a polarity which is alternated at a frequency of less than or equal to 1000 Hz.

A method and apparatus for forming a semiconductor device are provided. The method includes thermally treating a substrate having one or more silicon nanosheets formed thereon. Thermally treating the substrate includes positioning the substrate in a processing volume of a first processing chamber, the substrate having one or more silicon nanosheets formed thereon. Thermally treating the substrate further includes heating the substrate to a first temperature of more than about 250 degrees Celsius, generating hydrogen radicals using a remote plasma source fluidly coupled with the processing volume, and maintaining the substrate at the first temperature while concurrently exposing the one or more silicon nanosheets to the generated hydrogen radicals. The generated hydrogen radicals remove residual germanium from the one or more silicon nanosheets.

A method of forming regrown fiducials includes providing a III-V compound substrate having a device region and an alignment mark region. The III-V compound substrate is characterized by a processing surface. The method also includes forming a hardmask layer having a first set of openings in the device region exposing a first surface portion of the processing surface of the III-V compound substrate and a second set of openings in the alignment mark region exposing a second surface portion of the processing surface and etching the first surface portion and the second surface portion of the III-V compound substrate using the hardmask layer as a mask to form a plurality of trenches. The method also includes epitaxially regrowing a semiconductor layer in the trenches to form the regrown fiducials extending to a predetermined height over the processing surface in the alignment mark region.

Methods for forming a CPODE structure with reduced leakage current are disclosed herein. The CPODE structure is formed by etching away a pair of fins and forming a pair of trenches in the substrate where the pair of fins was originally located. A leakage path may be present in the area between the pair of fins. The etching is performed by cycling continuously plasma etch until the trenches are formed. The plasma etch removes any byproducts that may be formed during the fin etch which could reduce or stop the etching of the fins, the area between the pair of fins, and the substrate.

Exemplary substrate processing systems may include a chamber body defining a transfer region. The systems may include a lid plate seated on the chamber body. The lid plate may define a plurality of apertures. The systems may include a plurality of lid stacks. The systems may include a plurality of substrate supports. The systems may include a plurality of peripheral valves. Each peripheral valve may be disposed in one of the processing regions. Each peripheral valve may include a bottom plate coupled with the chamber body. The peripheral valve may include a bellow. The bellow may be coupled with the bottom plate. The peripheral valve may include a sealing ring having a body defining a central aperture. A bottom surface of the body may be coupled with the bellow. The body may define a recess having a diameter greater than that of a support plate of a substrate support.

A method of manufacturing a semiconductor device includes reducing a thickness of a device wafer bonded to a carrier wafer, wherein the device wafer includes a device, a portion of the carrier wafer beyond the device, in a plan view, is called a non-bonding area, and a portion of the carrier wafer overlapping the device, in the plan view, is called a device area. The method further includes performing an etching process on the non-bonding area of the carrier wafer, wherein the etching process is performed completely outside the device area of the carrier wafer.

An etching method includes (a) providing a substrate having a first silicon containing film and a second silicon containing film including at least a silicon containing film of which type is different from the first silicon containing film, on a substrate support in a chamber, (b) supplying a processing gas including a HF gas and a phosphorus containing gas into the chamber, and (c) etching the first silicon containing film and the second silicon containing film by generating plasma from the processing gas in the chamber by a source RF signal and generating a bias potential on the substrate by a bias signal.

A finFET device includes a doped source and/or drain extension that is disposed between a gate spacer of the finFET and a bulk semiconductor portion of the semiconductor substrate on which the n-doped or p-doped source or drain extension is disposed. The doped source or drain extension is formed by a selective epitaxial growth (SEG) process in a cavity formed proximate the gate spacer. After formation of the cavity, advanced processing controls (APC) (i.e., integrated metrology) is used to determine the distance of recess, without exposing the substrate to an oxidizing environment. The isotropic etch process, the metrology, and selective epitaxial growth may be performed in the same platform.

A resist underlayer film-forming composition includes: a polymer; and a solvent, in which the polymer has, in a side chain, one or two or more polymerizable multiple bonds selected from the group consisting of a carbon-carbon double bond, a carbon-carbon triple bond, a carbon-nitrogen double bond, and a carbon-nitrogen triple bond.