A method of manufacturing a semiconductor package of stacked semiconductor chips includes forming a reverse wire bond by bonding one end of a reverse wire to a chip pad of the second-highest semiconductor chip of the stacked semiconductor chips and connecting the other end of the reverse wire to a conductive bump on a chip pad of the uppermost semiconductor chip of the stacked semiconductor chips. The method also includes molding the stacked semiconductor chips with the reverse wire bond using a mold layer. The method further includes processing the mold layer to expose the conductive bump and the other end of the reverse wire in the reverse wire bond through an upper surface of the mold layer.

According to one embodiment, a semiconductor chip includes a first electrode, a semiconductor layer, a second electrode, a third electrode, and a metallic layer. The semiconductor layer includes a first portion, a second portion, and a third portion that is located between the first portion and the second portion. The semiconductor layer is provided on a first side of the first electrode in a first direction. The second electrode is over the first portion in the first direction. The third electrode is over the second portion in the first direction. The metallic layer is provided on a second side of the first electrode and is under the third portion in the first direction.

A package substrate and a semiconductor package including the same are provided. The semiconductor package includes a package substrate including a base having a front side and a back side, rear pads below the back side of the base, lower connection patterns below the rear pads and in contact with the rear pads, first and second front pads on the front side of the base, a first support pattern on the front side of the base having a thickness greater than a thickness of each of the first and second front pads, and a protective insulating layer on the front side of the base and having openings exposing the first and second front pads respectively, and on an upper surface and a side surface of the first support pattern; a lower semiconductor chip on the protective insulating layer of the package substrate, spaced apart from the first support pattern in a horizontal direction; and a first upper semiconductor chip on the package substrate vertically overlapping the lower semiconductor chip and the first support pattern.

A semiconductor package includes a first substrate, a first semiconductor chip, a first bonding wire, a second substrate, a second semiconductor chip and a second bonding wire. The first substrate has a window through a center portion of the first substrate. The first semiconductor chip is located on the first substrate. The first bonding wire is in the window of the first substrate and electrically connects to the first semiconductor chip and the first substrate. The second substrate is located on the first semiconductor chip, and has a window through a center portion of the second substrate. The second substrate electrically connects to the first substrate. The second semiconductor chip is located on the second substrate. The second bonding wire is in the window of the second substrate and electrically connects to the second semiconductor chip and the second substrate.

A semiconductor package includes a package substrate having an upper surface, a lower surface opposite to the upper surface, and a receiving groove that extends from the upper surface, toward the lower surface, by a predetermined depth; a first semiconductor chip in the receiving groove and protruding from the upper surface of the package substrate to have a predetermined height from the upper surface of the package substrate; an underfill member in the receiving groove and between the first semiconductor chip and an inner surface of the receiving groove; a plurality of second semiconductor chips sequentially stacked on the first semiconductor chip; and a molding member on the package substrate and covering the first semiconductor chip and the plurality of second semiconductor chips.

Implementations of an image sensor package may include an image sensor die including at least one bond pad thereon; a bond wire wirebonded to the at least one bond pad; and an optically transmissive lid coupled to the image sensor die with an optically opaque film adhesive over the at least one bond pad. The bond wire may extend through the optically opaque film adhesive to the at least one bond pad.

A semiconductor package including a package substrate defining a cavity therein; a first semiconductor chip on the package substrate; a first bump between the package substrate and the first semiconductor chip, the first bump electrically connecting the package substrate and the first semiconductor chip; a second semiconductor chip on the package substrate, the second semiconductor chip being at least partially in the cavity; a first bonding wire electrically connecting the package substrate and the second semiconductor chip; and an underfill layer covering the first bump and at least a portion of the first bonding wire.

A semiconductor package includes a package substrate, a processor chip mounted on a first region of the package substrate, a plurality of memory chips mounted on a second region of the package substrate being spaced apart from the first region of the package substrate, a signal transmission device mounted on a third region of the package substrate between the first and second regions of the package substrate, and a plurality of first bonding wires connecting the plurality of memory chips to the signal transmission device. The signal transmission device includes upper pads connected to the plurality of first bonding wires, penetrating electrodes arranged in a main body portion of the signal transmission device and connected to the upper pads, and lower pads in a lower surface portion of the signal transmission device and connected to the penetrating electrodes and connected to the package substrate via bonding balls.

A semiconductor package includes a package substrate including an upper pad on an upper surface of the package substrate, a first chip structure including a plurality of first chips offset-stacked in a first direction, a controller chip on the package substrate and apart from the first chip structure in a horizontal direction, a chip connection bump between the package substrate and the controller chip, and an underfill material layer covering the chip connection bump, wherein a side surface of the underfill material layer is perpendicular to the package substrate.

A package structure includes a package substrate. Numerous leads penetrate the package substrate. A top plate is disposed on the package substrate. An extension component extends from the top plate to the package substrate. Four side plates are disposed between the package substrate and the top plate. A die is disposed on the package substrate. The die includes a first surface and a second surface, and the first surface and the second surface are opposite. The extension component is bonded to the first surface of the die through a thermal conductive adhesive. Numerous conductive terminals are disposed on the die and exposed through the first surface. Numerous wires are disposed on the package substrate. Each wire is connected to one of the leads and one of the conductive terminals.