A method of fabricating an electronic device includes forming an embedded die frame having a cavity and a routing structure, a semiconductor die in the cavity with a gallium nitride layer on the routing structure, and a heat spreader having a thermally conductive insulator layer and a metal plate, the thermally conductive insulator layer having a first side that faces the embedded die frame and an opposite second side that faces away from the embedded die frame, with a portion of the first side of the thermally conductive insulator layer extending over a side of a silicon substrate of the semiconductor die, and the metal plate on the second side of the thermally conductive insulator layer.

The present disclosure relates to a multi-level three-dimensional (3D) package with multiple package levels vertically stacked. Each package level includes a redistribution structure and a die section over the redistribution structure. Each die section includes a thinned die that includes substantially no silicon substrate and has a thickness between several micrometers and several tens of micrometers, a mold compound, and an intermediary mold compound. Herein, the thinned die and the mold compound are deposed over the redistribution structure, the mold compound surrounds the thinned die and extends vertically beyond a top surface of the thinned die to define an opening over the thinned die and within the mold compound, the intermediary mold compound resides over the thinned die and fills the opening within the inner mold compound, such that a top surface of the intermediary mold compound and a top surface of the mold compound are coplanar.

An electronic device according to the present invention includes: a semiconductor chip that is mounted on a substrate; a heat sink that is attached to the substrate so as to face the upper surface of the semiconductor chip; a liquid metal that comes into contact with the upper surface of the semiconductor chip and the lower surface of the heat sink; seal members that are provided so as to surround the liquid metal and that seal an area between the upper surface of the substrate and the lower surface of the heat sink; and communication sections that are provided in the heat sink and communicate the internal space surrounded by the seal members, the semiconductor ship, and the heat sink, with the outside of the heat sink.

According to one aspect, a semiconductor package structure is provided. The semiconductor package structure includes: a plurality of first semiconductor chips arranged as being stacked along a first direction, the first semiconductor chip includes at least one first conductive structure, the first conductive structure includes a first connection structure extending along the first direction, a second connection structure extending along the first direction, and an interconnection structure between the first connection structure and the second connection structure in the first direction, and the interconnection structure is connected with both the first connection structure and the second connection structure; and a first bump connection layer between two adjacent ones of the first semiconductor chips in the first direction, the first bump connection layer includes at least one first bump structure, and the first bump structure is coupled with each of the first conductive structures in the two adjacent first semiconductor chips.

A method includes bonding a first plurality of device dies onto a wafer, wherein the wafer includes a second plurality of device dies, with each of the first plurality of device dies bonded to one of the second plurality of device dies. The wafer is then sawed to form a die stack, wherein the die stack includes a first device die from the first plurality of device dies and a second device die from the second plurality of device dies. The method further includes bonding the die stack over a package substrate.

Various embodiments of the teachings herein include a sintered power electronic module with a first plane and a second plane different from the first plane. An example comprises: a first substrate with a first metallization arranged on the first plane; a second substrate with a second metallization arranged on the second plane; a switchable die having a first power terminal and a second power terminal, the die arranged between the first substrate and the second substrate; and a surface area of all the sintered connections of the first plane is between 90 and 110% of a surface area of all the sintered connections of the second plane. The first power terminal of the die is joined to the first metallization via a sintered connection in the first plane and the second power terminal is joined to the second metallization via a sintered connection in the second plane.

An electronic module includes at least one electronic component including a first principal surface, first and second electrodes on the first principal surface, a wiring board including a second principal surface, third and fourth electrodes on the second principal surface, and a conductive resin portion. The conductive resin portion includes at least one first conductive resin portion joining the first and third electrodes, and at least one second conductive resin portion joining the second and fourth electrodes. The electronic module further includes at least one reinforcing resin portion that is disposed between at least one first and at least one second conductive resin portions and joins the first principal surface of the electronic component with the second principal surface of the wiring board.

A package structure includes a first dielectric layer disposed on a first patterned circuit layer, a first conductive via in the first dielectric layer and electrically connected to the first patterned circuit layer, a circuit layer on the first dielectric layer, a second dielectric layer on the first dielectric layer and covering the circuit layer, a second patterned circuit layer on the second dielectric layer and including conductive features, a chip on the conductive features, and a molding layer disposed on the second dielectric layer and encapsulating the chip. The circuit layer includes a plurality of portions separated from each other and including a first portion and a second portion. The number of pads corresponding to the first portion is different from that of pads corresponding to the second portion. An orthographic projection of each portion overlaps orthographic projections of at least two of the conductive features.

This invention provides opportunity for diamond and bi-wafer microstructures to be implemented in advanced ICs and advanced IC packages to form a new breed of ICs and SiPs that go beyond the limitations of silicon at the forefront of IC advancement due primarily to diamond's extreme heat dissipating ability. Establishing the diamond and bi-wafer microstructure capabilities and implementing them in advanced ICs and advanced IC packages gives IC and package architects and designers an extra degree of design freedom in achieving extreme IC performance, particularly when thermal management presents a challenge. Diamond's extreme heat spreading ability can be used to dissipate hotspots in processors and other high-power chips such as GaN HEMT, resulting in performance and reliability enhancement for IC and package applications covering HPC, AI, photonics, 5G RF/mmWave, power and IoT, and at the system level propelling the migration from traditional computing to near-memory computing and in-memory computing.

A printed wiring board assembly is disclosed that includes a printed wiring board with a first side and a second side opposite first side. Magnet structures are in physical contact with the printed wiring board and a microelectronic device component is coupled to the first side of the printed wiring board. A heat spreader overlies and is in thermal communication with the microelectronic device component, and posts are coupled to the heat spreader and horizontally neighbor the microelectronic device component, where the posts are in magnetic communication with the magnet structures. Related methods and electronic systems are also disclosed.