A semiconductor package may include a first redistribution substrate, a first semiconductor chip and a second semiconductor chip, which are mounted on the first redistribution substrate and are horizontally spaced apart from each other, a first mold layer provided to surround the first and second semiconductor chips and expose bottom surfaces of the first and second semiconductor chips, a bridge chip mounted on the bottom surfaces of the first and second semiconductor chips, a second mold layer provided on the first redistribution substrate to embed the first and second semiconductor chips, the first mold layer, and the bridge chip, a second redistribution substrate disposed on the second mold layer, an upper package mounted on the second redistribution substrate, and a vertical connection structure provided adjacent to the first mold layer to connect the first and second redistribution substrates to each other. The first redistribution substrate may have a recess provided in a top surface of the first redistribution substrate, and the bridge chip may be disposed in the recess.

Provided is a semiconductor package including: a substrate including a first surface a and second surface opposite to the first surface, the substrate further including a first cavity extending from the first surface to the second surface; first and second lower semiconductor chips, wherein the first and second lower semiconductor chips are vertically stacked in the first cavity; a first redistribution substrate on the first surface of the substrate; a first upper semiconductor chip on the first redistribution substrate; a second upper semiconductor chip on the first redistribution substrate and horizontally spaced apart from the first upper semiconductor chip; and a first bridge chip in the first redistribution substrate that connects the first and second upper semiconductor chips, wherein the first lower semiconductor chip is spaced apart from the first redistribution substrate, and wherein the second lower semiconductor chip is directly connected to the first redistribution substrate.

An electronic device is provided. The electronic device includes an electronic unit and a circuit structure. The circuit structure is electrically connected to the electronic unit. The circuit structure includes a first conductive layer, a first insulating layer and a first heat dissipation element. The first insulating layer is disposed between the first conductive layer and the electronic unit. The first heat dissipation element is in contact with the first conductive layer. Moreover, a heat transfer coefficient of the first dissipation element is greater than a heat transfer coefficient of the first insulating layer and less than a heat transfer coefficient of the first conductive layer.

A semiconductor package includes a redistribution structure including a redistribution insulating layer and a redistribution pattern, a first semiconductor device mounted on the redistribution structure, vertical connection conductors on the redistribution structure and apart from the first semiconductor device in a horizontal direction, a second semiconductor device mounted on the vertical connection conductors, and a heat-dissipation plate mounted on the first semiconductor device, wherein the heat-dissipation plate includes a main body and a plurality of protrusions protruding from the main body in the horizontal direction.

Semiconductor packages, and methods for manufacturing semiconductor packages are provided. In one aspect, a method of manufacturing a semiconductor package includes stacking a plurality of semiconductor chips including a first semiconductor chip and a second semiconductor chip, the first semiconductor ship being offset from the second semiconductor ship to expose upper connection pads; forming a multilayered photoresist film to cover the plurality of semiconductor chips; forming a plurality of openings by exposing and developing the multilayered photoresist film; forming a plurality of conductive posts by filling the plurality of openings with a conductive material; removing the multilayered photoresist film; forming a molding encapsulant to surround the plurality of semiconductor chips and the plurality of conductive posts; and forming a wiring structure electrically connected to the plurality of conductive posts. The multilayered photoresist film comprises at least two layers having different chemical resistances and resolutions.

An under bump metallurgy (UBM) and redistribution layer (RDL) routing structure includes an RDL formed over a die. The RDL comprises a first conductive portion and a second conductive portion. The first conductive portion and the second conductive portion are at a same level in the RDL. The first conductive portion of the RDL is separated from the second conductive portion of the RDL by insulating material of the RDL. A UBM layer is formed over the RDL. The UBM layer includes a conductive UBM trace and a conductive UBM pad. The UBM trace electrically couples the first conductive portion of the RDL to the second conductive portion of the RDL. The UBM pad is electrically coupled to the second conductive portion of the RDL. A conductive connector is formed over and electrically coupled to the UBM pad.

Various aspects of this disclosure provide a semiconductor device and a method of manufacturing a semiconductor device. As a non-limiting example, various aspects of this disclosure provide a semiconductor device comprising a stacked die structure and a method of manufacturing thereof.

The present invention discloses an elastic heat spreader for chip packaging, a packaging structure and a packaging method. The heat spreader includes a top cover plate and a side cover plate that extends outward along an edge of the top cover plate, wherein the top cover plate is configured to be placed on a chip, and at least a partial region of the side cover plate is an elastic member; and the elastic member at least enables the side cover plate to be telescopic in a direction perpendicular to the top cover plate. According to the present invention, a following problem is solved: delamination between the heat spreader and a substrate as well as the chip due to stress generated by different thermal expansion coefficients of the substrate, the heat spreader and the chip in a packaging process of a large-size product.

A method of manufacturing a semiconductor device includes: adhering together a heat generating body and a heat dissipating body via a thermally conductive sheet by applying a pressure on the heat generating body and the heat dissipating body in a thickness direction of the thermally conductive sheet with the thermally conductive sheet disposed therebetween, the thermally conductive sheet having a compression modulus of 1.40 MPa or less under a compressive stress of 0.10 MPa at 150 C., and a tack strength of 5.0 N.Math.mm or more at 25 C.

A stacked transistor arrangement and process of manufacture thereof are provided. Switched electrodes of first and second transistor chips are accessible on opposite sides of the first and second transistor chips. The first and second transistor chips are stacked one on top of the other. Switched electrodes of adjacent sides of the transistor chips are coupled together by a conductive layer positioned between the first and second transistor chips. Switched electrodes on sides of the first transistor chip and the second transistor chip that are opposite the adjacent sides are coupled to a lead frame by bond wires or solder bumps.