A method of manufacturing a semiconductor package of stacked semiconductor chips includes forming a reverse wire bond by bonding one end of a reverse wire to a chip pad of the second-highest semiconductor chip of the stacked semiconductor chips and connecting the other end of the reverse wire to a conductive bump on a chip pad of the uppermost semiconductor chip of the stacked semiconductor chips. The method also includes molding the stacked semiconductor chips with the reverse wire bond using a mold layer. The method further includes processing the mold layer to expose the conductive bump and the other end of the reverse wire in the reverse wire bond through an upper surface of the mold layer.

A package structure includes a circuit substrate, a semiconductor package, a first ring structure and a second ring structure. The semiconductor package is disposed on and electrically connected to the circuit substrate. The first ring structure is attached to the circuit substrate and surrounding the semiconductor package, wherein the first ring structure includes a central opening and a plurality of corner openings extending out from corners of the central opening, the semiconductor package is located in the central opening, and the plurality of corner openings is surrounding corners of the semiconductor package.

A package substrate and a semiconductor package including the same are provided. The semiconductor package includes a package substrate including a base having a front side and a back side, rear pads below the back side of the base, lower connection patterns below the rear pads and in contact with the rear pads, first and second front pads on the front side of the base, a first support pattern on the front side of the base having a thickness greater than a thickness of each of the first and second front pads, and a protective insulating layer on the front side of the base and having openings exposing the first and second front pads respectively, and on an upper surface and a side surface of the first support pattern; a lower semiconductor chip on the protective insulating layer of the package substrate, spaced apart from the first support pattern in a horizontal direction; and a first upper semiconductor chip on the package substrate vertically overlapping the lower semiconductor chip and the first support pattern.

The invention provides an integrated circuit device and an adaptive power scaling method thereof to reduce and optimize power consumption. The integrated circuit device includes a first die and a second die, wherein the first die and the second die are stacked into a three-dimensional structure. A power circuit provides a power voltage to a first interface circuit of the first die and a second interface circuit of the second die. The first interface circuit transmits data to the second interface circuit via a die-to-die transfer circuit. The control logic controls the power circuit to adjust the power voltage provided to the first interface circuit and the second interface circuit based on the signal quality of the data received by the second interface circuit.

A method of manufacturing a semiconductor package may include disposing, in a lower mold, a substrate strip in which a plurality of semiconductor chips are arranged in a horizontal direction, providing, in an upper mold, a release film to which a first encapsulant is attached, allowing the upper mold and the lower mold to be proximate to each other such that a first encapsulant is adjacent to an upper surface of each of the plurality of semiconductor chips, injecting a second encapsulant into a space between the upper mold and the lower mold, heating the first encapsulant and the second encapsulant to form a molded structure including a first encapsulating layer and a second encapsulating layer, allowing the upper mold and the lower mold to be spaced from each other such that the molded structure is separated from the release film, and cutting the molded structure.

A semiconductor package includes a redistribution structure, a first semiconductor chip above the redistribution structure, a second semiconductor chip on, and offset relative to, the first semiconductor chip, a plurality of first conductive posts extending from a bottom surface of the second semiconductor chip to a top surface of the redistribution structure, a third semiconductor chip on the second semiconductor chip, a plurality of second conductive posts extending from a bottom surface of the third semiconductor chip to the top surface of the redistribution structure, and a molding layer between the top surface of the redistribution structure and the bottom surface of the third semiconductor chip.

A semiconductor package may include a first substrate, semiconductor dies stacked on the first substrate in a direction perpendicular to a top surface of the first substrate to have a stepwise structure, a mold layer disposed on the first substrate to cover the semiconductor dies, a second substrate disposed on the mold layer, and vertical conductive lines electrically connecting the semiconductor dies to the second substrate. The first substrate may include a first region and a second region. The first region may have a first thermal expansion coefficient, and the second region may have a second thermal expansion coefficient. The first thermal expansion coefficient may be different from the second thermal expansion coefficient.

A semiconductor assembly, a packaging structure, and associated method for corner stress reduction in semiconductor devices. The assembly includes a plurality of semiconductor dies and a plurality of spacers. Each spacer in the plurality of spacers is disposed between and configured to separate two semiconductor dies in the plurality of semiconductor dies. At least one spacer in the plurality of spacers has at least one extended spacer corner feature configured to extend toward at least one corner of at least one semiconductor die in the plurality of semiconductor dies disposed adjacent to the at least one spacer. At least one extended spacer corner feature is configured to reduce stress on at least one semiconductor die.

A method of repairing a display panel and a repaired display panel are provided. The display panel includes a panel substrate, a plurality of micro LEDs arranged on the panel substrate, and a molding member covering the plurality of micro LEDs. The molding member includes a first molding member and a second molding member disposed in a region surrounded by the first molding member. The second molding member has a composition or a shape different from that of the first molding member, and the second molding member surrounds at least one side surface of the plurality of micro LEDs.

A semiconductor device includes first, second and third stacked chips with a first, second and third substrate, respectively, at least three first, second and third logical circuits, respectively, and at least two first, second and third vias, respectively, and a fourth chip stacked on the third chip having a fourth substrate, and at least three fourth logical circuits. First and second ones of the first to third logical circuits of the first to fourth chips are each configured to perform a first and second logical operation, respectively, on a first and second address input signal, respectively, received at the respective chip to thereby output a first and second address output signal, respectively. Third ones are each configured to activate the respective chip based on at least the second address output signal transmitted within the respective chip.