A method of manufacturing a semiconductor package of stacked semiconductor chips includes forming a reverse wire bond by bonding one end of a reverse wire to a chip pad of the second-highest semiconductor chip of the stacked semiconductor chips and connecting the other end of the reverse wire to a conductive bump on a chip pad of the uppermost semiconductor chip of the stacked semiconductor chips. The method also includes molding the stacked semiconductor chips with the reverse wire bond using a mold layer. The method further includes processing the mold layer to expose the conductive bump and the other end of the reverse wire in the reverse wire bond through an upper surface of the mold layer.

An offset interposer includes a land side including land-side ball-grid array (BGA) and a package-on-package (POP) side including a POP-side BGA. The land-side BGA includes two adjacent, spaced-apart land-side pads, and the POP-side BGA includes two adjacent, spaced-apart POP-side pads that are coupled to the respective two land-side BGA pads through the offset interposer. The land-side BGA is configured to interface with a first-level interconnect. The POP-side BGA is configured to interface with a POP substrate. Each of the two land-side pads has a different footprint than the respective two POP-side pads.

A semiconductor and a method of fabricating the semiconductor having multiple, interconnected die including: providing a semiconductor substrate having a plurality of disparate die formed within the semiconductor substrate, and a plurality of scribe lines formed between pairs of adjacent die of the plurality of disparate die; and fabricating, by a lithography system, a plurality of inter-die connections that extend between adjacent pair of die of the plurality of die.

A method of manufacturing a semiconductor package includes manufacturing dies on each of wafers, testing the wafers including the dies, calculating total scores for the wafers according to results of the tests, and setting reference values corresponding to semiconductor products. The method also includes classifying, as the semiconductor product, a selected wafer having a total score corresponding to a selected reference value among the reference values. The method further includes packaging the dies included in the selected wafer.

An electronic package includes an electronic component including terminals, a plurality of surface contacts, at least some of the surface contacts being electrically coupled to the terminals within the electronic package, a mold compound covering the electronic component and partially covering the surface contacts with a bottom surface exposed from the mold compound, and a plurality of wires extending from exposed surfaces of the surface contacts, each of the wires providing a solderable surface for mounting the electronic package at a standoff on an external board.

The invention provides improved techniques for bonding devices using copper-to-copper or other types of bonds. A substrate is cleaned to remove surface oxides and contaminants and then rinsed. The rinsed substrate is provided to coating unit where a protective coating is applied to the substrate. The protective coating may be applied by immersing the substrate in a bath or via chemical vapor deposition. In an aspect, the protective coating may be copper selective so that the protective coating is only applied to copper features of the substrate. The protective coating minimizes formation of oxides and other bond weakening forces that may form during bonding processes, such as bonding a copper wire to a copper bond pad of the substrate. In an aspect, an annealing process is used to cure the protective coating and remove small imperfections and other abnormalities in the protective coating prior to the bonding process.

A semiconductor package includes a substrate, a first semiconductor die disposed on the substrate, a second semiconductor die stacked on the first die and offset from it in a first direction and a second direction that are perpendicular to each other, and a third semiconductor die stacked on the first and second dies and offset from them in the first direction. The first semiconductor die includes a first pad and a second pad, arranged successively in the second direction. The second semiconductor die includes a third pad and a fourth pad, and the third semiconductor die includes a fifth pad and a sixth pad, each arranged successively in the second direction. A first conductive pattern connects the first and fifth pads, while a second conductive pattern connects the second, fourth, and sixth pads. The first and second conductive patterns are spaced apart from the third pad.