A semiconductor package includes a package substrate including first and second power P-pads and first and second signal P-pads, a lower layer chip including first and second power L-pads and first and second signal L-pads, an upper layer chip offset from the lower layer chip and including first and second power U-pads and first and second signal U-pads. The first power and signal P-pads are alternatingly stacked, the first power and signal L-pads are alternatingly stacked, and the first power and signal U-pads are alternatingly stacked. The second power and signal P-pads are alternatingly stacked, the second power and signal L-pads are alternatingly stacked, and the second power and signal U-pads are alternatingly stacked. Bonding wires connect the first and second power U-pads, the first and second power L-pads, the second power U-pads and P-pads, and the second signal U-pads and P-pads.

A semiconductor package includes a substrate including first bonding pads. At least one chip stack is on the substrate and includes a plurality of semiconductor chips stacked thereon. The semiconductor chips include first connection pads electrically connected to the first bonding pads, bonding wires electrically connecting the substrate to the chip stack, and connection bumps below the substrate. The semiconductor chips include a second group of semiconductor chips stacked on a first group of semiconductor chips. An uppermost semiconductor chip in the first group of semiconductor chips or a lowermost semiconductor chip in the second group of semiconductor chips further includes second connection pads electrically connected to the first connection pads, respectively. The bonding wires include first bonding wires electrically connecting the first connection pads of the semiconductor chips to each other, and second bonding wires electrically connecting the second connection pads and the first bonding pads to each other.

The present disclosure relates to a semiconductor package. A semiconductor package according to implementations of the present disclosure includes a package substrate and a chip stack including semiconductor chips sequentially stacked on the package substrate. Each of the semiconductor chips includes a first side surface provided on one side of a virtual central line perpendicular to an upper surface of the package substrate and passing through a center of the chip stack and also a second side surface provided on the other side of the virtual central line. Odd-numbered semiconductor chips among the stacked semiconductor chips include heat source circuits adjacent to the first side surfaces, and even-numbered semiconductor chips among the stacked semiconductor chips include heat source circuits adjacent to the second side surfaces.

A semiconductor package includes: a first redistribution structure; a first chip disposed on the first redistribution structure; a molding member at least partially surrounding the first chip and disposed on the first redistribution structure; a plurality of conductive pillars penetrating the molding member in a vertical direction; a support structure disposed between adjacent conductive pillars of the plurality of conductive pillars and disposed on the first redistribution structure; a second redistribution structure disposed on the molding member, the plurality of conductive pillars, and the support structure; a second chip disposed on the second redistribution structure and overlapping the plurality of conductive pillars; and a heat dissipation chip overlapping the first chip in the vertical direction.

A semiconductor package includes a package substrate, a first semiconductor chip on an upper surface of the package substrate, a spacer chip on the upper surface of the package substrate and spaced apart from the first semiconductor chip, a plurality of second semiconductor chips sequentially stacked on the spacer chip by a plurality of adhesive films, respectively, and a molding member on the spacer chip, the first semiconductor chip, and the plurality of second semiconductor chips. When viewed in a plan view, the spacer chip has an overlapping region overlapping with a lowermost second semiconductor chip of the plurality of second semiconductor chips. The lowermost second semiconductor chip is attached to the spacer chip by a first adhesive film. A portion of the first adhesive film attached to the spacer chip is within a recess that is in an upper surface of the overlapping region of the spacer chip.

A three-dimensional semiconductor memory device may include a substrate, a stack structure including interlayer dielectric layers and gate electrodes alternately and repeatedly stacked on the substrate, and vertical channel structures provided in vertical channel holes penetrating the stack structure. Each of the vertical channel structures may include a data storage pattern covering an inner side surface of each of the vertical channel holes, a vertical semiconductor pattern covering the data storage pattern, and a gapfill insulating pattern filling an internal space enclosed by the vertical semiconductor pattern. The vertical semiconductor pattern may have a first surface which is in contact with the gapfill insulating pattern, and a second surface which is in contact with the data storage pattern. A germanium concentration in the vertical semiconductor pattern may decrease in a direction from the first surface toward the second surface.

A semiconductor package includes: a lower substrate; a semiconductor chip disposed on the lower substrate; an upper substrate disposed on the semiconductor chip, having a lower surface facing the semiconductor chip, and including step structures disposed below the lower surface; a connection structure disposed around the semiconductor chip and connecting the lower substrate to the upper substrate; and an encapsulant filling a space between the lower substrate and the upper substrate and sealing at least a portion of each of the semiconductor chip and the connection structure. The lower surface of the upper substrate has a first surface portion on which the step structures are disposed and a second surface portion having a step with respect to the lower surface of the step structures, and the second surface portion extends between opposite edges of the upper substrate.

A power semiconductor module includes an AC bus bar having a first side that faces a first substrate and a second side that faces a second substrate. A first power transistor die has a drain terminal connected to a first metallic region of the first substrate and a source terminal connected to the first side of the AC bus bar. A second power transistor die has a drain terminal connected to the second side of the AC bus bar and a source terminal connected to a first metallic region of the second substrate. First and second DC bus bars are connected to the first metallic region of the respective substrates, vertically overlap one another, and protrude from a first side of a mold body that encapsulates the power transistor dies. The AC bus bar protrudes from a different side of the mold body as the DC bus bars.

A wafer-on-wafer bonded memory and logic device can enable high bandwidth transmission of data directly between a memory die and a logic die. A memory device formed on a memory die can include many global input/output lines and many arrays of memory cells. Each array of memory cells can include respective local input/output (LIO) lines coupled to a global input/output line. A logic device can be formed on a logic die. A bond, formed between the memory die and the logic die via a wafer-on-wafer bonding process, can couple the many global input/output lines to the logic device.

The present disclosure provides a memory system packaging structure and fabrication methods. The memory system packaging structure includes memory modules, a memory controller, a redistribution layer electrically connected to the memory controller, a plastic encapsulation layer encapsulating the memory modules and the memory controller, and one or more connecting pillars extending in the vertical direction and configured for providing electric power to the memory modules. Each memory module includes memory dies stacked in a vertical direction. Each connecting pillar includes a first portion being in physical contact with one of the memory dies and a second portion being in physical contact with the redistribution layer.