Provided is a semiconductor device including a substrate, a source/drain area on the substrate, a first interlayer insulating film on the substrate, a contact plug penetrating at least a portion of the first interlayer insulating film along a first direction perpendicular to a surface of the substrate and electrically connected to the source/drain area, a second interlayer insulating film on the first interlayer insulating film, a wiring via penetrating a portion of the second interlayer insulating film along the first direction and electrically connected to the contact plug, a wiring line penetrating at least a portion of the second interlayer insulating film along the first direction and electrically connected to the wiring via, and a protecting film between the wiring via and the second interlayer insulating film and between the wiring line and the second interlayer insulting film.

The present application discloses a semiconductor device and a method for fabricating the same. The semiconductor device includes a first substrate including a front side and a back side; a first passivation layer over the front side; a second passivation layer over the back side and having a top surface; a conductive feature in the first passivation layer; a through substrate via (TSV) penetrating through the second passivation layer and the first substrate and electrically coupled to the conductive feature; and a polymer liner between the TSV and the first substrate, wherein the polymer liner has a top surface lower than the top surface of the second passivation layer; a barrier layer between the second passivation layer and the TSV, between the polymer liner and the TSV, and between the interconnect structure and the TSV; and an adhesion layer between the barrier layer and the TSV.

An integrated circuit device includes a middle insulating structure on a substrate, a first contact structure passing through the middle insulating structure and extending by a first vertical length from a top surface of the middle insulating structure toward the substrate, and a second contact structure passing through the middle insulating structure. The middle insulating structure may have a top surface extending in a lateral direction at a first vertical level. The second contact structure may extend by a second vertical length greater than the first vertical length from the top surface of the middle insulating structure toward the substrate. The first contact structure may have a first top surface extending planar along an extension line of the top surface of the middle insulating structure. The second contact structure may have a second top surface, which may be convex in a direction away from the substrate.

An apparatus that includes a first conductive pattern positioned at a first wiring layer and extending in a first direction, a second conductive pattern positioned at a second wiring layer located above the first wiring layer and extending in a second direction crossing the first direction, and a contact plug connecting the first conductive pattern with the second conductive pattern. The contact plug includes a lower conductive section contacting the first conductive pattern and an upper conductive section contacting the second conductive pattern. A maximum width of the upper conductive section in the first direction is smaller than a maximum width of the lower conductive section in the first direction.

The present disclosure provides a manufacturing method of a semiconductor structure including the following steps. A trench is formed between bit lines. A seed layer is deposited in the trench, and a first contact layer is deposited on the seed layer in the trench. A second contact layer is deposited on the first contact layer to fill the trench, in which a second doping concentration of the second contact layer is lower than a first doping concentration of the first contact layer. An annealing process is performed on the first contact layer and the second contact layer, such that dopants in the first contact layer diffuse into the second contact layer to form a contact plug including the first contact layer and the second contact layer.

Methods of forming microelectronic devices comprise forming a dielectric layer on a substrate, the dielectric layer comprising at least one feature defining a gap including sidewalls and a bottom. The methods include forming a hardmask on the dielectric layer; selectively depositing a self-assembled monolayer (SAM) on the bottom of the gap and on the hardmask; treating the microelectronic device with a plasma to remove the self-assembled monolayer (SAM) from the hardmask; forming a barrier layer on the dielectric layer and on the hardmask; selectively depositing a metal liner on the barrier layer on the sidewall; and performing a gap fill process on the metal liner.

Methods of forming devices comprise forming a dielectric material on a substrate, the dielectric layer comprising at least one feature defining a gap including sidewalls and a bottom. The methods include passivating a metal material at a bottom of the gap with an alkyl reactant to form a passivation layer on the metal material, the gap defined by the bottom and sidewalls comprising the dielectric material with having a barrier layer thereon. A metal liner is selectively deposited on the barrier layer on the sidewall over the passivation layer on the bottom.

An oxide film etching method includes: forming a protective film of a metal or a metal nitride that does not contain silicon so as to cover a protection target film, among the protection target film containing silicon and a silicon-containing oxide film exposed on a surface of a substrate; supplying, to the substrate, a mixed gas including a hydrogen fluoride gas and an ammonia gas to react with the silicon-containing oxide film, and modifying the oxide film to generate a reaction product; and sublimating and removing the reaction product.