A bonded structure is disclosed. The bonded structure can include a substrate. The bonded structure can include a first memory unit disposed on the substrate. The first memory unit can have a first stack of memory dies and a first logic controller disposed on the first stack. The first logic controller can manage data communicated to or from the first stack of memory dies. The bonded structure can also include a processor die hybrid bonded to the first memory unit along a bonding interface and a vertical interconnect connecting the substrate to the processor die. The bonded structure can further include a second memory unit disposed on the substrate. The second memory unit can include a second stack of memory dies and a second logic controller disposed on the second stack. The second logic controller can manage data communicated to or from the second stack of memory dies.

A memory device includes a substrate, a gate line contact electrically connected to a gate line selected from among the gate lines, a conductive wiring structure connected to the gate line contact, and bonding pads arranged on the conductive wiring structure. The bonding pads include a first bonding pad, a second bonding pad, a third bonding pad apart from the first bonding pad in the first horizontal direction, and a fourth bonding pad apart from the first bonding pad in a second horizontal direction perpendicular to the first horizontal direction. The conductive wiring structure electrically connects the first bonding pad and the second bonding pad to the gate line contact, and the second bonding pad is arranged diagonally between the first horizontal direction and the second horizontal direction with respect to the first bonding pad.

In an embodiment, a device includes: a first integrated circuit die comprising a semiconductor substrate and a first through-substrate via; a gap-fill dielectric around the first integrated circuit die, a surface of the gap-fill dielectric being substantially coplanar with an inactive surface of the semiconductor substrate and with a surface of the first through-substrate via; a dielectric layer on the surface of the gap-fill dielectric and the inactive surface of the semiconductor substrate; a first bond pad extending through the dielectric layer to contact the surface of the first through-substrate via, a width of the first bond pad being less than a width of the first through-substrate via; and a second integrated circuit die comprising a die connector bonded to the first bond pad.

A method includes bonding a first wafer to a second wafer; after bonding the first wafer to the second wafer, bonding a third wafer to the first wafer; conducting a process control monitor on the first and second wafers via a first electrical pathway that traverses an interface between the first and second wafers; determining whether a charge present at the interface between the first and second wafers.

According to one aspect of the present disclosure, a semiconductor structure is provided. The semiconductor structure may include a first semiconductor chip and a second semiconductor chip that are bonded along a first direction. The first semiconductor chip may include a first semiconductor layer. The first semiconductor chip may include a plurality of first connection structures extending through the first semiconductor layer along the first direction. A dielectric material may be between and in contact with any two of the first connection structures. The first semiconductor chip and the second semiconductor chip may be coupled by a plurality of first bonding contacts and the plurality of first connection structures. The plurality of first bonding contacts may extend through a first dielectric layer. The first connection structure may be coupled with the first bonding contact.

A semiconductor device may include a transistor on a substrate, a first wiring structure on the transistor, a first bonding pad structure on the first wiring structure, a second wiring structure on the first wiring structure and at least partially overlapping the first bonding pad structure in a horizontal direction, a second bonding pad structure on and spaced apart from the second wiring structure and overlapping the first bonding pad structure in the horizontal direction, a bit line structure on the first and second bonding pad structures, a gate structure on the bit line structure, a channel adjacent to the gate structure and in contact with the bit line structure, and a capacitor on the channel.

A semiconductor package includes a wiring structure. A buffer die is disposed on the wiring structure. A logic die is disposed alongside the buffer die on the wiring structure. A first encapsulating material covers at least a portion of each of the buffer die and the logic die. A memory stack is disposed on the buffer die and is electrically connected to the buffer die. A bridge die is disposed so as to extend over at least a portion of each of the buffer die and the logic die, and is electrically connected to each of the buffer die and the logic die. A second encapsulating material covers at least a portion of each of the memory stack and the bridge die. The buffer die and the logic die are disposed at a level that is between those of the wiring structure and the bridge die.

A semiconductor device with a two-sided redistribution layer is disclosed. The semiconductor device comprises a host device and one or more memory stack cubes. A redistribution layer is disposed between and couples the host device and the memory stack cubes. This redistribution layer features an edge surface extending between the host device and the memory stack cubes. The semiconductor device includes first connective circuitry that extends through the redistribution layer, is coupled with the host device, and is exposed at the edge surface of the redistribution layer. Additionally, second connective circuitry extends through the redistribution layer, is coupled with the memory stack cubes, and is exposed at the edge surface of the redistribution layer. Connective structures couple the first and second connective circuitry exposed at the edge surface of the redistribution layer.

Methods, systems, and devices for a stacked semiconductor system are described. The stacked semiconductor system may include a semiconductor die on a redistribution layer (RDL) and a polymer material at least partially surrounding the semiconductor die. A silicon nitride material may be above the semiconductor die and on the polymer material. A logic die may be hybrid bonded with a bonding material on the silicon nitride material. And a conductive post may extend at least partially through the silicon nitride material and the polymer material and may couple the logic die with the RDL.

A memory device includes a lower source-level semiconductor layer, a source contact layer, and an upper source-level semiconductor layer, an alternating stack of insulating layers and electrically conductive layers, a memory opening vertically extending through the alternating stack, the upper source-level semiconductor layer, and the source contact layer, and a memory opening fill structure located in the memory opening and including a memory film and a vertical semiconductor layer having a surface segment that contacts the source contact layer. In one embodiment, the upper source-level semiconductor layer may be locally thickened to provide sufficient etch resistance during formation of a lateral isolation trench. In another embodiment, a sacrificial line trench fill structure may be employed as an etch stop structure during formation of a lateral isolation trench.