A semiconductor package includes a first semiconductor chip including a first semiconductor substrate having a first active surface and a first inactive surface opposite to each other, a plurality of through electrodes penetrating the first semiconductor substrate, and a rear cover layer covering the first inactive surface, a second semiconductor chip stacked on the first semiconductor chip and including a second semiconductor substrate having a second active surface and a second inactive surface opposite to each other, and a front cover layer covering the second active surface, a plurality of signal pad structures penetrating the rear cover layer and the front cover layer to be electrically connected to the plurality of through electrodes, and a plurality of dummy pad structures apart from the plurality of signal pad structures in a horizontal direction, and penetrating the rear cover layer and the front cover layer.

The present discloses includes a memory device including a first vertical plug and a second vertical plug that are arranged to be adjacent to each other, a first select line contacting the first vertical plug, a second select line over a same layer as the first select line and contacting the second vertical plug, and an isolation pattern overlapping with a portion of the first vertical plug and a portion of the second vertical plug and separating the first select line from the second select line.

A semiconductor die stack includes a first semiconductor die having a first lattice direction, and a second semiconductor die bonded to the first semiconductor die and having a second lattice direction different than the first lattice direction.

A display device according to the present invention, includes: a first substrate including a first single-crystal semiconductor substrate provided with a plurality of light emitting portions and with a first drive circuit that drives the plurality of light emitting portions, wherein the first single-crystal semiconductor substrate includes a plurality of light guiding portions that transmit light so as to implement a see-through function.

A stacked semiconductor device is disclosed that includes a plurality of semiconductor dies. Each die has oppositely disposed first and second surfaces, with pads formed on each of the surfaces. A plurality of through-vias connect respective pads on the first surface to respective pads on the second surface. The through-vias include a first group of through-vias coupled to respective I/O circuitry on the semiconductor die and a second group of through-vias not coupled to I/O circuitry on the semiconductor die. The plurality of semiconductor dies are stacked such that the first group of through-vias in a first one of the plurality of semiconductor dies are aligned with respective ones of at least a portion of the second group of through-vias in a second one of the plurality of semiconductor dies.

A semiconductor device may include a gate structure including conductive layers and insulating layers that are alternately stacked; a first contact plug including a first main portion extended by a first depth through the gate structure and a first extension portion connected to the first main portion and having a sidewall with a staircase shape, the first contact plug being electrically connected to a first conductive layer of the conductive layers; and a second contact plug including a second main portion extended by a second depth greater than the first depth through the gate structure and a second extension portion connected to the second main portion and having a sidewall with a staircase shape, the second contact plug being electrically connected to a second conductive layer of the conductive layers, wherein the second extension portion may have a greater width than the first extension portion.

A semiconductor device including high-integrated memory cells and a method for fabricating the semiconductor device is provided. The method may include forming a first bonding dielectric layer on a substrate, sequentially forming a mold stack, a blocking layer, and a second bonding dielectric layer on a sacrificial substrate to create a stack structure, flipping the stack structure including the sacrificial substrate, bonding the first bonding dielectric layer and the second bonding dielectric layer, removing the sacrificial substrate from the stack structure, and forming a plurality of memory cells vertically stacked in the mold stack of the stack structure, using the blocking layer as a barrier.

Disclosed is a bonded structure including an element with a bonding surface, the bonding surface having a dielectric region and a first semiconductor region laterally spaced from the dielectric region. The bonded structure further includes a first die directly bonded to the dielectric region of the element without an intervening adhesive. The bonded structure further includes a second die having a second bonding surface having a second semiconductor region, the second semiconductor region being bonded to the first semiconductor region of the element without an intervening adhesive and without an intervening deposited dielectric material.

A non-volatile memory device is provided, including a first bit line, a second bit line, a first page buffer including a first erase transistor connected to the first bit line via a first bonding pad, and a second page buffer including a second erase transistor connected to the second bit line via a second bonding pad, and a plurality of bonding pads including a first bonding pad and a second bonding pad. The first erase transistor is driven based on a first erase control signal and is connected between the first bit line and the first erase voltage line. The second erase transistor is driven based on a first erase control signal and is connected between the second bit line and the second erase voltage line different from the first erase voltage line. The first bonding pad and the second bonding pad are disposed adjacent to each other.

A semiconductor device includes a capacitor on a first substrate, a channel on the capacitor, a gate electrode at least partially overlapping the channel in a horizontal direction, a bit line structure on the gate electrode and the channel, a first wiring structure on the bit line structure, a bonding pad structure on the first wiring structure, a second wiring structure on the bonding pad structure, a second substrate on the second wiring structure, a transistor beneath the second substrate, a third wiring structure on the second substrate, an isolation pattern extending through the second substrate, and a through via extending through the isolation pattern.